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MPC5643L微控制器参考手册
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"MPC5643LRM.pdf - Freescale Semiconductor的MPC5643L微控制器参考手册,版本10"
MPC5643L微控制器是Freescale Semiconductor推出的一款高性能嵌入式处理器,适用于需要强大处理能力和高级功能的汽车、工业和其他应用。该参考手册详细介绍了MPC5643L及其衍生产品MPC5643L RMC的主要特性和功能。
1. **概述**
- MPC5643L微控制器:是一款基于e200z4d内核的高性能MCU,提供了广泛的外设和内存选项,适用于实时控制和数据处理任务。
- MPC5643L设备概览:概括了该设备的主要硬件配置和功能特性。
- 设备块图:展示了一个详细的系统架构,包括各个组件之间的连接和交互。
2. **功能总结**
- 高性能e200z4d核心:提供强大的计算能力,支持复杂的软件算法和实时操作。
- Crossbar开关(XBAR):允许灵活的数据传输路径,优化系统性能。
- 内存保护单元(MPU):确保内存区域的安全,防止意外访问或修改。
- 增强型直接存储器访问(eDMA):高效地管理数据传输,减轻CPU负担。
- 带有ECC的片上闪存:提供错误检测和纠正,增强数据可靠性。
- 带有ECC的片上SRAM:同样具备错误检测和纠正功能,确保关键数据的稳定性。
- 平台闪存控制器:管理和控制外部存储设备,提高访问效率。
- 平台静态RAM控制器(SRAMC):管理SRAM资源,优化读写速度。
- 存储子系统的访问时间:详细描述了不同内存类型和位置的访问延迟。
- 错误校正状态模块(ECSM):监测并报告内存和其他关键部件的错误。
- 外设桥接器(PBRIDGE):连接并协调各种外围设备的通信。
- 中断控制器(INTC):管理系统的中断请求,确保及时响应。
- 系统时钟和时钟生成:描述了内部时钟源和频率调节机制。
- 频率调制相位锁定环(FMPLL):提供灵活的频率合成,支持多种工作模式。
此参考手册为设计者提供了全面的硬件指南,包括详细的寄存器描述、接口规范、编程模型等,是开发基于MPC5643L平台的嵌入式系统的关键参考资料。通过深入理解和利用这些特性,开发者可以构建出高效、可靠且功能丰富的应用系统。
MPC5643L Microcontroller Reference Manual, Rev. 10
16 Freescale Semiconductor
27.2 Overview .......................................................................................................................................901
27.3 Features .........................................................................................................................................901
27.4 Memory map .................................................................................................................................902
27.5 Register descriptions .....................................................................................................................902
27.5.1 Control Register (CR) ...................................................................................................902
27.5.2 Modulation Register (MR) ...........................................................................................905
27.6 Functional description ...................................................................................................................906
27.6.1 Normal mode ................................................................................................................906
27.6.2 Progressive clock switching .........................................................................................906
27.6.3 Normal Mode with frequency modulation ...................................................................907
27.6.4 Powerdown mode .........................................................................................................908
27.7 Requirements .................................................................................................................................908
27.8 Recommendations .........................................................................................................................909
Chapter 28
Interrupt Controller (INTC)
28.1 Introduction ...................................................................................................................................911
28.1.1 Module overview ..........................................................................................................911
28.1.2 Block diagram ..............................................................................................................911
28.1.3 Features .........................................................................................................................912
28.2 Modes of Operation .......................................................................................................................913
28.2.1 Normal Mode ................................................................................................................913
28.2.2 Debug Mode .................................................................................................................914
28.2.3 Stop Mode ....................................................................................................................914
28.2.4 Factory Test Mode ........................................................................................................914
28.3 External Signal Description ..........................................................................................................914
28.4 Memory map/register definition ....................................................................................................914
28.4.1 Memory map ................................................................................................................914
28.4.2 Register Information .....................................................................................................915
28.4.3 INTC Block Configuration Register (INTC_BCR) .....................................................916
28.4.4 INTC Current Priority Register for Processor 0 (INTC_CPR_PRC0) .........................917
28.4.5 INTC Interrupt Acknowledge Register for Processor 0 (INTC_IACKR_PRC0) ........918
28.4.6 INTC End of Interrupt Register for Processor 0 (INTC_EOIR_PRC0) .......................919
28.4.7 INTC Software Set/Clear Interrupt Registers (INTC_SSCIR0_3 - INTC_SSCIR4_7) .....
919
28.4.8 INTC Priority Select Registers (INTC_PSR0_3 - INTC_PSR252_255) .....................921
28.5 Functional Description ..................................................................................................................922
28.5.1 Interrupt Request Sources .............................................................................................922
28.5.2 Priority Management ....................................................................................................923
28.5.3 Handshaking with processor .........................................................................................924
28.6 Initialization/application information ............................................................................................927
28.6.1 Initialization flow .........................................................................................................927
28.6.2 Interrupt exception handler ...........................................................................................927
28.6.3 Code Compression’s Impact on Vector Table ..............................................................929
28.6.4 ISR, RTOS, and Task Hierarchy ...................................................................................929
MPC5643L Microcontroller Reference Manual, Rev. 10
Freescale Semiconductor 17
28.6.5 Order of Execution .......................................................................................................930
28.6.6 Priority Ceiling Protocol ...............................................................................................931
28.6.7 Selecting Priorities According to Request Rates and Deadlines ..................................932
28.6.8 Software settable Interrupt Requests ............................................................................933
28.6.9 Lowering Priority Within an ISR .................................................................................934
28.6.10 Negating an Interrupt Request Outside of its ISR ........................................................934
28.6.11 Examining LIFO contents ............................................................................................935
28.7 Interrupt sources ............................................................................................................................935
Chapter 29
JTAG Controller (JTAGC)
29.1 Introduction ...................................................................................................................................945
29.1.1 Overview ......................................................................................................................945
29.1.2 Features .........................................................................................................................945
29.1.3 Modes of operation .......................................................................................................946
29.2 External signal description ............................................................................................................947
29.2.1 Overview ......................................................................................................................947
29.2.2 Detailed Signal Descriptions ........................................................................................947
29.3 Register Definition ........................................................................................................................948
29.3.1 Register descriptions ....................................................................................................948
29.4 Functional Description ..................................................................................................................951
29.4.1 JTAGC Reset Configuration .........................................................................................951
29.4.2 IEEE 1149.1-2001 (JTAG) Test Access Port ................................................................951
29.4.3 TAP Controller State Machine .....................................................................................952
29.4.4 JTAGC Block Instructions ............................................................................................954
29.4.5 Boundary Scan ..............................................................................................................956
29.5 Initialization/Application Information ..........................................................................................956
Chapter 30
LIN Controller (LINFlexD)
30.1 Introduction ...................................................................................................................................957
30.2 Main features .................................................................................................................................957
30.2.1 LIN mode features ........................................................................................................958
30.2.2 UART mode features ....................................................................................................958
30.3 The LIN protocol ...........................................................................................................................959
30.3.1 Dominant and recessive logic levels ............................................................................959
30.3.2 LIN frames ....................................................................................................................959
30.3.3 LIN header ....................................................................................................................960
30.3.4 Response .......................................................................................................................961
30.4 LINFlexD and software intervention ............................................................................................962
30.5 Summary of operating modes .......................................................................................................962
30.6 Controller-level operating modes ..................................................................................................963
30.6.1 Initialization mode ........................................................................................................963
30.6.2 Normal mode ................................................................................................................964
30.6.3 Sleep (low-power) mode ..............................................................................................964
MPC5643L Microcontroller Reference Manual, Rev. 10
18 Freescale Semiconductor
30.7 LIN modes .....................................................................................................................................964
30.7.1 Master mode .................................................................................................................964
30.7.2 Slave mode ...................................................................................................................966
30.7.3 Slave mode with identifier filtering ..............................................................................968
30.7.4 Slave mode with automatic resynchronization .............................................................971
30.8 Test modes .....................................................................................................................................973
30.8.1 Loop Back mode ...........................................................................................................973
30.8.2 Self Test mode ..............................................................................................................973
30.9 UART mode ..................................................................................................................................974
30.9.1 Data frame structure .....................................................................................................974
30.9.2 Buffer ............................................................................................................................975
30.9.3 UART transmitter .........................................................................................................976
30.9.4 UART receiver ..............................................................................................................977
30.10Memory map and register description ...........................................................................................979
30.10.1 LIN control register 1 (LINCR1) .................................................................................980
30.10.2 LIN interrupt enable register (LINIER) .......................................................................983
30.10.3 LIN status register (LINSR) .........................................................................................985
30.10.4 LIN error status register (LINESR) ..............................................................................988
30.10.5 UART mode control register (UARTCR) .....................................................................989
30.10.6 UART mode status register (UARTSR) .......................................................................992
30.10.7 LIN timeout control status register (LINTCSR) ..........................................................994
30.10.8 LIN output compare register (LINOCR) ......................................................................995
30.10.9 LIN timeout control register (LINTOCR) ....................................................................996
30.10.10 LIN fractional baud rate register (LINFBRR) ..............................................................997
30.10.11 LIN integer baud rate register (LINIBRR) ...................................................................997
30.10.12 LIN checksum field register (LINCFR) .......................................................................998
30.10.13 LIN control register 2 (LINCR2) .................................................................................999
30.10.14 Buffer identifier register (BIDR) ................................................................................1000
30.10.15 Buffer data register least significant (BDRL) ............................................................1001
30.10.16 Buffer data register most significant (BDRM) ...........................................................1002
30.10.17 Identifier filter enable register (IFER) ........................................................................1003
30.10.18 Identifier filter match index (IFMI) ............................................................................1003
30.10.19 Identifier filter mode register (IFMR) ........................................................................1004
30.10.20 Identifier filter control registers (IFCR0–IFCR15) ....................................................1005
30.10.21 Global control register (GCR) ....................................................................................1006
30.10.22 UART preset timeout register (UARTPTO) ...............................................................1007
30.10.23 UART current timeout register (UARTCTO) .............................................................1008
30.10.24 DMA Tx enable register (DMATXE) .........................................................................1009
30.10.25 DMA Rx enable register (DMARXE) ........................................................................1009
30.11 DMA interface .............................................................................................................................1010
30.11.1 Master node, TX mode ...............................................................................................1010
30.11.2 Master node, RX mode ...............................................................................................1013
30.11.3 Slave node, TX mode .................................................................................................1015
30.11.4 Slave node, RX mode .................................................................................................1018
30.11.5 UART node, TX mode ...............................................................................................1021
MPC5643L Microcontroller Reference Manual, Rev. 10
Freescale Semiconductor 19
30.11.6 UART node, RX mode ...............................................................................................1023
30.11.7 Use cases and limitations ............................................................................................1026
30.12Functional description .................................................................................................................1027
30.12.1 8-bit timeout counter ..................................................................................................1027
30.12.2 Interrupts .....................................................................................................................1028
30.12.3 Fractional baud rate generation ..................................................................................1029
30.13Programming considerations .......................................................................................................1031
30.13.1 Master node ................................................................................................................1031
30.13.2 Slave node ..................................................................................................................1032
30.13.3 Extended frames .........................................................................................................1036
30.13.4 Timeout .......................................................................................................................1037
30.13.5 UART mode ................................................................................................................1037
Chapter 31
Memory Protection Unit (MPU)
31.1 Introduction .................................................................................................................................1039
31.2 Block diagram .............................................................................................................................1039
31.3 Features .......................................................................................................................................1041
31.4 Modes of operation ......................................................................................................................1042
31.5 External signal description ..........................................................................................................1042
31.6 Memory map and register definition ...........................................................................................1042
31.6.1 MPU Control/Error Status Register (MPU_CESR) ...................................................1044
31.6.2 MPU Error Address Register, Slave Port n (MPU_EARn) ........................................1045
31.6.3 MPU Error Detail Register, Slave Port n (MPU_EDRn) ...........................................1045
31.6.4 MPU Region Descriptor n (MPU_RGDn) .................................................................1046
31.6.5 MPU Region Descriptor Alternate Access Control n (MPU_RGDAACn) ...............1051
31.7 Functional description .................................................................................................................1052
31.7.1 Access evaluation macro ............................................................................................1053
31.7.2 Putting it all together and AHB error terminations ....................................................1055
31.8 Initialization information .............................................................................................................1056
31.9 Application information ..............................................................................................................1056
Chapter 32
Mode Entry Module (MC_ME)
32.1 Introduction .................................................................................................................................1059
32.1.1 Overview ....................................................................................................................1059
32.1.2 Features .......................................................................................................................1061
32.1.3 Modes of operation .....................................................................................................1061
32.2 External signal description ..........................................................................................................1062
32.3 Memory map and register definition ...........................................................................................1062
32.3.1 Memory map ..............................................................................................................1063
32.3.2 Register description ....................................................................................................1070
32.4 Functional description .................................................................................................................1090
32.4.1 Mode Transition Request ............................................................................................1090
32.4.2 Mode details ...............................................................................................................1092
MPC5643L Microcontroller Reference Manual, Rev. 10
20 Freescale Semiconductor
32.4.3 Mode transition process ..............................................................................................1096
32.4.4 Protection of mode configuration registers ................................................................1104
32.4.5 Mode Transition Interrupts .........................................................................................1104
32.4.6 Peripheral Clock Gating .............................................................................................1106
32.4.7 Application example ...................................................................................................1107
Chapter 33
Nexus Crossbar Slave Port Data Trace Module (NXSS)
[cut2/3 only]
33.1 Introduction .................................................................................................................................1109
33.2 Block diagram .............................................................................................................................1109
33.3 Features .......................................................................................................................................1110
33.4 External signal description ..........................................................................................................1110
33.4.1 Rules for output messages ..........................................................................................1110
33.4.2 Auxiliary port arbitration ............................................................................................1110
33.5 NXSS programmer model ...........................................................................................................1111
33.5.1 Development Control Registers (DC1 and DC2) .......................................................1111
33.5.2 Watchpoint Trigger Register (WT) .............................................................................1113
33.5.3 Data Trace Control Register (DTC) ...........................................................................1113
33.5.4 Data Trace Start Address Registers 1 and 2 (DTSA1 and DTSA2) ...........................1115
33.5.5 Data Trace End Address Registers 1 and 2 (DTEA1 and DTEA2) ............................1115
33.5.6 Breakpoint / Watchpoint Control Register 1 (BWC1) ................................................1115
33.5.7 Breakpoint / Watchpoint Control Register 2 (BWC2) ................................................1116
33.5.8 Breakpoint/Watchpoint Address Registers 1 and 2 (BWA1 and BWA2) ...................1117
33.5.9 Unimplemented registers ............................................................................................1117
33.6 Functional description .................................................................................................................1117
33.6.1 TCODEs supported by NXSS_0 and NXSS_1 ..........................................................1117
33.6.2 Data Trace ...................................................................................................................1119
33.6.3 Data Trace Messaging (DTM) ...................................................................................1119
33.6.4 DTM Message Formats ..............................................................................................1119
33.6.5 DTM operation ...........................................................................................................1122
33.7 Watchpoint support .....................................................................................................................1122
33.7.1 Watchpoint messaging ................................................................................................1123
33.7.2 Watchpoint error message ..........................................................................................1123
Chapter 34
Nexus Port Controller (NPC)
34.1 Information specific to this device ..............................................................................................1125
34.1.1 Parameter values .........................................................................................................1125
34.1.2 Unavailable features ...................................................................................................1125
34.2 Introduction .................................................................................................................................1125
34.2.1 Overview ....................................................................................................................1126
34.2.2 Features .......................................................................................................................1126
34.2.3 Modes of operation .....................................................................................................1127
34.3 External signal description ..........................................................................................................1128
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