TI SN75DP159：6Gbps DP转HDMI转换器技术文档

DP转HDMI

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SN65DP159

SN75DP159

www.ti.com.cn

ZHCSE15F –JULY 2015–REVISED MAY 2018

7.7 HDMI and DVI TMDS Output Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Single-ended high level output voltage

Data rate ≤ 1.65-Gbps; PRE_SEL =

NC; TX_TERM_CTL = H;

SLEW_CTL = H; OE = H; DR = 750-

Mbps, VSadj = 7.06-kΩ

– 10 V

+ 10

1.65-Gbps < Data rate ≤ 3.4-Gbps;

PRE_SEL = NC; TX_TERM_CTL =

H; SLEW_CTL = H; OE = H; DR =

2.97-Gbps, VSadj = 7.06-kΩ

– 200 V

+ 10

Single-ended high level output voltage

3.4-Gbps < Data rate < 6 Gbps;

PRE_SEL = NC; TX_TERM_CTL = L;

SLEW_CTL = H; OE = H; DR = 6-

Gbps, VSadj = 7.06-kΩ

– 400 V

+ 10 mV

Single-ended low level output voltage

Data rate ≤ 1.65-Gbps; PRE_SEL =

NC; TX_TERM_CTL = H;

SLEW_CTL = H; OE = H; DR = 750-

Mbps, VSadj = 7.06-kΩ

– 600 V

– 400

1.65-Gbps < Data rate ≤ 3.4-Gbps;

PRE_SEL = NC; TX_TERM_CTL =

H; SLEW_CTL = H; OE = H; DR =

2.97-Gbps, VSadj = 7.06-kΩ

– 700 V

– 400

Single-ended low level output voltage

3.4-Gbps < Data rate < 6-Gbps;

PRE_SEL = NC; TX_TERM_CTL = L;

SLEW_CTL = H; OE = H; DR = 6-

Gbps

– 1000 V

– 400 mV

SWING_DA

Single-ended output voltage swing on

data lane

PRE_SEL = NC; TX_TERM_CTL =

H/NC/L; SLEW_CTL = H; OE = H;

DR = 270-Mbs/2.97/6Gbps VSadj =

7.06-kΩ

400 500 600 mV

SWING_CLK

Single-ended output voltage swing on

clock lane

Data rate ≤ 3.4-Gbps; PRE_SEL =

NC; TX_TERM_CTL = H;

SLEW_CTL = H; OE = H; VSadj =

7.06-kΩ

400 500 600

Data rate > 3.4-Gbps; PRE_SEL =

NC; TX_TERM_CTL = NC;

SLEW_CTL = H; OE = H; VSadj =

7.06-kΩ

200 300 400

ΔV

SWING

Change in single-end output voltage

swing per 100 Ω ΔVsadj

20 mV

ΔV

OCM(SS)

Change in steady state output common

mode voltage between logic levels

–5 5 mV

OD(PP)

Output differential voltage before pre-

emphasis

Vsadj = 7.06-kΩ; PRE_SEL = Z, See

图 8

800 1200 mV

OD(SS)

Steady-state output differential voltage

Vsadj = 7.06-kΩ; PRE_SEL = L, See

图 9

600 1050 mV

LEAK

Failsafe condition leakage current

= 0-V; V

= 0-V; output pulled

to 3.3 V through 50-Ω resistors

45 µA

Short circuit current limit Main link output shorted to GND 50 mA

TERM

Source termination resistance for HDMI

2.0

75 150 Ω

SN65DP159

SN75DP159

ZHCSE15F –JULY 2015–REVISED MAY 2018

www.ti.com.cn

7.8 AUX, DDC, and I

C Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input capacitance AUX data rate = 1-MHz 10 pF

AUX AC coupling capacitance 75 200 nF

R(AUX)

Data rate of the AUX channel input 0.8 1 1.2 Mbps

I-DC(AUX)

DC input voltage on AUX channel,

AUX_SRCp/n: 100-kΩ pull up to 3.6 V

but differential common mode is 2 V

or less.

-0.5 3.6 V

AUX_DIFF_PP_TX

Peak-to-peak differential voltage at

TX pins

AUX_DIFF_PP

= 2 × |V

AUXP

– V

AUXN

| 0.29 1.38 V

AUX_DIFF_PP_RX

Peak-to-peak differential voltage at

RX pins

AUX_DIFF_PP

= 2 × |V

AUXP

– V

AUXN

| 0.14 1.36 V

AUX_DC_CM

AUX channel DC common mode

voltage

0 2 V

AUX_SHORT

AUX channel short circuit current limit 90 mA

I-DC

SCL/SDA_SNK DC input voltage –0.3 5.6 V

SCL/SDA_CTL, SCL/SDA_SRC DC

input voltage

-0.3 3.6 V

SCL/SDA_SNK, SCL/SDA_SRC Low

level input voltage

0.3 x V

SCL/SDA_CTL Low level input

voltage

0.3 x V

SCL/SDA_SNK high level input

voltage

3 V

SCL/SDA_SRC high level input

voltage

0.7 x V

SCL/SDA_CTL high level input

voltage

0.7 x V

SCL/SDA_CTL, SCL/SDA_SRC low-

level output voltage

= 3-mA and V

> 2-V 0.4 V

= 3-mA and V

< 2-V 0.2 V

SCL

SCL clock frequency fast I2C mode

for local I2C control

400 kHz

bus

Total capacitive load for each bus line

(DDC and local I2C pins)

400 pF

7.9 HPD Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level input voltage HPD_SNK 2.1 V

Low-level input voltage HPD_SNK 0.8 V

High-level output voltage I

= –500-µA; HPD_SRC 2.4 3.6 V

Low-level output voltage I

= 500-µA; HPD_SRC 0 0.1 V

LEAK

Failsafe condition leakage current VCC = 0-V; V

= 0-V; HPD_SNK = 5-V 40 μA

H_HPD

High-level input current

Device powered; V

= 5-V;

H_HPD

includes R

pdHPD

resistor current

40 μA

L_HPD

Low-level input current

Device powered; V

= 0.8-V;

L_HPD

includes R

pdHPD

resistor current

pdHPD

HPD input termination to GND V

= 0-V 150 190 220 kΩ

SN65DP159

SN75DP159

www.ti.com.cn

ZHCSE15F –JULY 2015–REVISED MAY 2018

7.10 HDMI and DVI Main Link Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

REDRIVER MODE

Data rate (Automatic Mode) 250 1000 Mbps

Data rate (full redriver mode) 250 6000 Mbps

PLH

Propagation delay time (low to high) 250 600 ps

PHL

Propagation delay time (high to low) 250 800 ps

Transition time (rise and fall time);

measured at 20% and 80% levels for data

lanes. TMDS clock meets t

for all three

times.

SLEW_CTL = H; TX_TERM_CTL = L;

PRE_SEL = NC; OE = H; DR = 6 Gbps

SLEW_CTL = L; TX_TERM_CTL = NC;

PRE_SEL = NC; OE = H; DR = 6 Gbps

SLEW_CTL = NC; TX_TERM_CTL =

NC; PRE_SEL = NC; OE = H; DR = 6

Gbps; CLK 150MHz

100

SK1(T)

Intra-pair output skew

SLEW_CTL = NC; TX_TERM_CTL =

NC; PRE_SEL = NC; OE = H; DR = 6

Gbps;

40 ps

SK2(T)

Inter-pair output skew

SLEW_CTL = NC; TX_TERM_CTL =

NC; PRE_SEL = NC; OE = H; DR = 6

Gbps;

100 ps

JITD1(1.4b)

Total output data jitter

DR = 2.97 Gbps, HDMI_SEL/A1 = NC,

EQ_SEL/A0 = NC; PRE_SEL = NC;

SLEW_CTL = H OE = H.

See 图 10 at TTP3

0.2 Tbit

JITD1(2.0)

Total output data jitter

3.4Gbps < Rbit ≤ 3.712Gps SLEW_CTL

= H; TX_TERM_CTL = NC; PRE_SEL =

NC; OE = H

0.4 Tbit

3.712Gbps < Rbit < 5.94Gbps

SLEW_CTL = H; TX_TERM_CTL = NC;

PRE_SEL = NC; OE = H

-0.033

2Rbit2

+0.23

Rbit +

0.1998

Tbit

5.94Gbps ≤ Rbit ≤ 6.0Gbps SLEW_CTL

= H; TX_TERM_CTL = NC; PRE_SEL =

NC; OE = H

0.8 Tbit

JITC1(1.4b)

Total output clock jitter CLK = 297 MHz 0.25 Tbit

JITC1(2.0)

Total output clock jitter DR = 6Gbps: CLK = 150 MHz 0.3 Tbit

RETIMER MODE

Data rate (Full retimer mode) 0.25 6 Gbps

Data rate (Automatic mode) 1.0 6 Gbps

XVR

Automatic redriver to retimer crossover

Measured with input signal applied from

0 to 200 mVpp

.75 1.0 1.25 Gbps

CROSSOVER

Crossover frequency hysteresis 250 MHz

LLBW

Data retimer PLL bandwidth Default loop bandwidth setting .4 1 MHz

ACQ

Input clock frequency detection and retimer

acquisition time

180 μs

JT1

Input clock jitter tolerance Tested when data rate > 1.0 Gbps 0.3 Tbit

Transition time (rise and fall time);

measured at 20% and 80% levels for data

lanes. TMDS clock meets t

for all three

times.

SLEW_CTL = H; TX_TERM_CTL = L;

PRE_SEL = NC; OE = H; DR = 6 Gbps

SLEW_CTL = L; TX_TERM_CTL = NC;

PRE_SEL = NC; OE = H; DR = 6 Gbps

SLEW_CTL = NC; TX_TERM_CTL =

NC; PRE_SEL = NC; OE = H; DR = 6

Gbps; CLK = 150 MHz

100

DCD

OUT_CLK ± duty cycle 40% 50% 60%

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