ARM系统开发指南：设计与优化实战

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《ARM系统开发者指南》是一本备受推崇的国外技术著作，专为深入理解与优化ARM处理器的系统软件设计而编写。本书由两位经验丰富的专家——安德鲁·斯洛斯（Andrew N. Sloss）和多米尼克·西默斯（Dominic Symes）联袂创作。斯洛斯先生拥有计算机科学学士学位，早在1987年就开始涉足ARM处理器领域，并在艾默生出版公司为中文和埃及象形文字设计了首套运行于ARM2和ARM3处理器的编辑系统。他的职业生涯跨越了16年以上，目前在ARM Inc.担任技术销售工程师，专注于为开发新产品的企业提供咨询和支持，主要在美国销售团队工作，位于加利福尼亚州洛杉矶。西默斯博士则在英国剑桥的ARM Ltd.担任软件工程师，自1995年起专注于基于ARM的嵌入式软件开发。他拥有牛津大学的数学学士和哲学博士学位，早在1989年就初次接触并编程ARM处理器。两人的专业知识和实战经验使得本书不仅理论扎实，而且富有实践性，对于想要深入ARM平台系统软件开发的读者来说，无论是硬件理解、软件优化，还是移植和性能调优，都提供了宝贵的指导。《ARM系统开发者指南》涵盖了广泛的议题，包括但不限于ARM处理器架构原理，操作系统内核设计，驱动程序开发，嵌入式系统软件开发最佳实践，以及针对ARM处理器特性的优化策略。书中详细阐述了如何设计高效能的实时操作系统，如何处理内存管理，以及如何利用硬件加速特性提升应用程序性能。此外，书中还可能涉及ARM指令集架构（ISA）、异常处理、调试工具和性能分析等方面的知识。对于那些希望在ARM平台上构建高性能、低功耗产品的工程师，这本书无疑是一本不可或缺的参考资料。它不仅适合初学者理解基础概念，也适合有经验的开发人员深化对ARM平台的理解，提升开发效率和产品质量。无论是在嵌入式设备、移动设备，还是物联网设备的软件开发过程中，《ARM系统开发者指南》都能提供有力的技术支持。

1.1 The RISC design philosophy

1.2 The ARM Design Philosophy

1.2.1 Instruction Set for Embedded Systems

1.3 Embedded System Hardware

1.3.1 ARM Bus Technology

1.3.2 AMBA Bus Protocol

1.3.3 Memory

1.3.4 Peripherals

1.4 Embedded System Software

1.4.1 Initialization (Boot) Code

1.4.2 Operating System

1.4.3 Applications

1.5

Summary

4 Chapter 1 ARM Embedded Systems

1.1 The RISC design philosophy

The ARM core uses a RISC architecture. RISC is a design philosophy aimed at delivering

simple but powerful instructions that execute within a single cycle at a high clock speed.

The RISC philosophy concentrates on reducing the complexity of instructions performed

by the hardware because it is easier to provide greater ﬂexibility and intelligence in software

rather than hardware. As a result, a RISC design places greater demands on the compiler.

In contrast, the traditional complex instruction set computer (CISC) relies more on the

hardware for instruction functionality, and consequently the CISC instructions are more

complicated. Figure 1.1 illustrates these major differences.

The RISC philosophy is implemented with four major design rules:

1. Instructions—RISC processors have a reduced number of instruction classes. These

classes provide simple operations that can each execute in a single cycle. The compiler

or programmer synthesizes complicated operations (for example, a divide operation)

by combining several simple instructions. Each instruction is a ﬁxed length to allow

the pipeline to fetch future instructions before decoding the current instruction. In

contrast, in CISC processors the instructions are often of variable size and take many

cycles to execute.

2. Pipelines—The processing of instructions is broken down into smaller units that can be

executed in parallel by pipelines. Ideally the pipeline advances by one step on each cycle

for maximum throughput. Instructions can be decoded in one pipeline stage. There is

no need for an instruction to be executed by a miniprogram called microcode as on

CISC processors.

3. Registers—RISC machines have a large general-purpose register set. Any register can

contain either data or an address. Registers act as the fast local memory store for all data

CISC RISC

Compiler

Processor Processor

Code

Generation

Greater

Com

lexit

Greater

Complexity

Code

Generation

Figure 1.1 CISC vs. RISC. CISC emphasizes hardware complexity. RISC emphasizes compiler

complexity.

1.2 The ARM Design Philosophy 5

processing operations. In contrast, CISC processors have dedicated registers for speciﬁc

purposes.

4. Load-store architecture—The processor operates on data held in registers. Separate load

and store instructions transfer data between the register bank and external memory.

Memory accesses are costly, so separating memory accesses from data processing pro-

vides an advantage because you can use data items held in the register bank multiple

times without needing multiple memory accesses. In contrast, with a CISC design the

data processing operations can act on memory directly.

These design rules allow a RISC processor to be simpler, and thus the core can operate

at higher clock frequencies. In contrast, traditional CISC processors are more complex

and operate at lower clock frequencies. Over the course of two decades, however, the

distinction between RISC and CISC has blurred as CISC processors have implemented

more RISC concepts.

1.2 The ARM Design Philosophy

There are a number of physical features that have driven the ARM processor design. First,

portable embedded systems require some form of battery power. The ARM processor has

been speciﬁcally designed to be small to reduce power consumption and extend battery

operation—essential for applications such as mobile phones and personal digital assistants

(PDAs).

High code density is another major requirement since embedded systems have lim-

ited memory due to cost and/or physical size restrictions. High code density is useful for

applications that have limited on-board memory, such as mobile phones and mass storage

devices.

In addition, embedded systems are price sensitive and use slow and low-cost memory

devices. For high-volume applications like digital cameras, every cent has to be accounted

for in the design. The ability to use low-cost memory devices produces substantial savings.

Another important requirement is to reduce the area of the die taken up by the embedded

processor. For a single-chip solution, the smaller the area used by the embedded processor,

the more available space for specialized peripherals. This in turn reduces the cost of the

design and manufacturing since fewer discrete chips are required for the end product.

ARM has incorporated hardware debug technology within the processor so that software

engineers can view what is happening while the processor is executing code. With greater

visibility, software engineers can resolve issues faster, which has a direct effect on the time

to market and reduces overall development costs.

The ARM core is not a pure RISC architecture because of the constraints of its primary

application—the embedded system. In some sense, the strength of the ARM core is that

it does not take the RISC concept too far. In today’s systems the key is not raw processor

speed but total effective system performance and power consumption.

6 Chapter 1 ARM Embedded Systems

1.2.1 Instruction Set for Embedded Systems

The ARM instruction set differs from the pure RISC deﬁnition in several ways that make

the ARM instruction set suitable for embedded applications:

■

Variable cycle execution for certain instructions—Not every ARM instruction executes

in a single cycle. For example, load-store-multiple instructions vary in the number

of execution cycles depending upon the number of registers being transferred. The

transfer can occur on sequential memory addresses, which increases performance since

sequential memory accesses are often faster than random accesses. Code density is also

improved since multiple register transfers are common operations at the start and end

of functions.

■

Inline barrel shifter leading to more complex instructions—The inline barrel shifter is

a hardware component that preprocesses one of the input registers before it is used

by an instruction. This expands the capability of many instructions to improve core

performance and code density. We explain this feature in more detail in Chapters 2, 3,

and 4.

■

Thumb 16-bit instruction set—ARM enhanced the processor core by adding a second

16-bit instruction set called Thumb that permits the ARM core to execute either

16- or 32-bit instructions. The 16-bit instructions improve code density by about

30% over 32-bit ﬁxed-length instructions.

■

Conditional execution—An instruction is only executed when a speciﬁc condition has

been satisﬁed. This feature improves performance and code density by reducing branch

instructions.

■

Enhanced instructions—The enhanced digital signal processor (DSP) instructions were

added to the standard ARM instruction set to support fast 16×16-bit multiplier oper-

ations and saturation. These instructions allow a faster-performing ARM processor in

some cases to replace the traditional combinations of a processor plus a DSP.

These additional features have made the ARM processor one of the most commonly

used 32-bit embedded processor cores. Many of the top semiconductor companies around

the world produce products based around the ARM processor.

1.3 Embedded System Hardware

Embedded systems can control many different devices, from small sensors found on

a production line, to the real-time control systems used on a NASA space probe. All

these devices use a combination of software and hardware components. Each component

is chosen for efﬁciency and, if applicable, is designed for future extension and expansion.

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