Serial ATA Revision 3.0 Gold Revision page 16 of 663
Figure 161 – Receiver Jitter and CM Tolerance Test – Setting TJ and CM Levels (Gen3i) ....... 294
Figure 162 – Receiver Jitter and CM Tolerance Test (Gen3i) .................................................... 294
Figure 163 – Return Loss Test-Calibration ................................................................................. 295
Figure 164 – Return Loss Test .................................................................................................... 297
Figure 165 – Intra-Pair Skew Test for a Transmitter ................................................................... 299
Figure 166 – Receiver Intra-Pair Skew Test—Setting Levels ..................................................... 299
Figure 167 – Receiver Intra-Pair Skew Test ............................................................................... 299
Figure 168 – Example Intra-Pair Skew test for Transmitter (10.8 pS) ........................................ 300
Figure 169 – TX/RX Sequencing Transient Voltage Measurement ............................................ 300
Figure 170 – AC Coupled Capacitance Measurement................................................................ 301
Figure 171 – Squelch Detector Threshold Test—Setting Levels ................................................ 303
Figure 172 – Squelch Detector Threshold Test........................................................................... 304
Figure 173 – TDR Differential Impedance Test—Setting Risetime............................................. 306
Figure 174 – TDR Impedance Test ............................................................................................. 306
Figure 175 – TDR Single-Ended Impedance Test—Setting Risetime ........................................ 307
Figure 176 – DC Coupled Common Mode Voltage Measurement.............................................. 307
Figure 177 – AC Coupled Common Mode Voltage Measurement.............................................. 308
Figure 178 – TDR Impedance Test ............................................................................................. 308
Figure 179 - Sequencing Transient Voltage Laboratory Load .................................................... 309
Figure 180 – OOB Signals........................................................................................................... 310
Figure 181 – Transmitter Examples ............................................................................................ 311
Figure 182 – Transmitter Examples (Concluded)........................................................................ 312
Figure 183 – COMRESET Sequence.......................................................................................... 313
Figure 184 – COMINIT Sequence ............................................................................................... 314
Figure 185 – OOB Signal Detector.............................................................................................. 316
Figure 186 – Squelch Detector.................................................................................................... 317
Figure 187 – Power-On Sequence.............................................................................................. 330
Figure 188 – PHYRDY to Partial—Host Initiated ........................................................................ 332
Figure 189 – PHYRDY to Partial—Device Initiated..................................................................... 333
Figure 190 – Nomenclature Reference ....................................................................................... 336
Figure 191 – Bit Ordering and Significance................................................................................. 346
Figure 192 – Transmission Structures ........................................................................................ 348
Figure 193 – FIS type value assignments ................................................................................... 383
Figure 194 – Register - Host to Device FIS layout ...................................................................... 384
Figure 195 – Register - Device to Host FIS layout ...................................................................... 386
Figure 196 – Set Device Bits - Device to Host FIS layout ........................................................... 387
Figure 197 – DMA Activate - Device to Host FIS layout.............................................................. 388
Figure 198 – DMA Setup – Device to Host or Host to Device FIS layout ................................... 389
Figure 199 – BIST Activate - Bidirectional................................................................................... 392
Figure 200 – PIO Setup - Device to Host FIS layout................................................................... 395
Figure 201 – Data – Host to Device or Device to Host FIS layout .............................................. 397
Figure 202 –DEVICE CONFIGURATION IDENTIFY data structure ........................................... 494
Figure 203 - DEVICE CONFIGURATION SET data structure .................................................... 495
Figure 204 – DMA Setup FIS definition for memory buffer selection .......................................... 501
Figure 205 – READ FPDMA QUEUED command definition....................................................... 504
Figure 206 – READ FPDMA QUEUED error on command receipt............................................. 506
Figure 207 - Set Device Bits FIS with error notification, and command completions ................. 507
Figure 208 - Set Device Bits FIS aborting all outstanding command.......................................... 508
Figure 209 – WRITE FPDMA QUEUED command definition ..................................................... 509
Figure 210 - Set Device Bits FIS for successful WRITE FPDMA QUEUED command completion
............................................................................................................................................. 510
Figure 211 – WRITE FPDMA QUEUED error on command receipt ........................................... 511
Figure 212 - Set Device Bits FIS with error notification, and command completions ................. 512
Figure 213 - NCQ QUEUE MANAGEMENT - Command definition ........................................... 513
Figure 214 – NCQ QUEUE MANAGEMENT, Abort NCQ Queue - Successful completion........ 515
Figure 215 – NCQ QUEUE MANAGEMENT, Abort NCQ Queue - error on command receipt .. 516