Functional Description
16 Revision 1
The memory interface for Core1553BRM allows a simple connection to a memory device. It can be
configured to connect to either synchronous or asynchronous memory devices. This allows the core to
be connected to synchronous logic or memory within the FPGA or to external memory blocks. The
interface supports a standard bus request and grant protocol, and provides a WAIT input, allowing the
core to interface to slow memory devices. This allows the core to share system memory rather than have
its own dedicated memory block.
Registers
Core1553BRM contains thirty-three 16-bit registers (Table 1-1). One of these is used to enable enhanced
Core1553BRM functions. The remaining 32 registers are used to control the core. The Control and
Operation registers are used to allow a CPU to set the core operating mode; BC, RT, MT, or combined
RT and MT. The function of the other registers varies depending on the operating mode.
Core Operation
Core1553BRM is designed to be software-compatible with existing 1553B solutions.
It supports the following features:
• Interrupt logs
• Programmable message timeouts
• Circular buffer operation
It does not support the following features:
• Buffer mode operation
• Built-in test functions, although the BIT register and the transmit BIT mode code are supported.
• Auto-initialization of internal registers and memory
Table 1-1 • Registers Address Map
Address Name
00 Control
01 Operation and Status
02 Current Command
03 Interrupt Mask
04 Pending Interrupt
05 Interrupt Pointer
06 Built-In Test (BIT) Register
07 Time Tag
08 Descriptor Pointer
09 1553B Status Word
10 Initialization Count
11 Monitor Command Pointer
12 Monitor Data Pointer
13 Monitor Block Count
14 Monitor Filter A
15 Monitor Filter B
16–31 RT Command Legalization
32 Enhanced Features
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