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"SSD1317控制芯片规格书及IC修订历史信息"

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The document "SSD1317 Advance Information" provides technical data and specifications for the Solomon Systech semiconductor, specifically the 0.96 inch OLED/PLED segment/common driver with controller. The document emphasizes that the information contained within is for a new product and is subject to change without notice, cautioning readers to refer to the Solomon Systech website for the most up-to-date information. The SSD1317 features a 128 x 96 dot matrix display and is designed for use in various electronic devices. It includes detailed information about the IC revision history and specifies the copyright information for the Solomon Systech Limited company. In addition, the document outlines the web address where readers can find further details and updates for the product. Overall, the document serves as a comprehensive guide for the SSD1317 control chip, providing detailed technical specifications and information for potential users and developers. It is a valuable resource for anyone seeking to incorporate the SSD1317 into their electronic designs.

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Solomon Systech

Dec 2015

P 10/32

Rev 1.0

SSD1317

Pin Name Pin Type

Description

D[7:0] I/O These pins are bi-directional data bus connecting to the MCU data bus.

Unused pins are recommended to tie LOW.

When serial interface mode is selected, D0 will be the seri

al clock input: SCLK; D1

will be the serial data input: SDIN.

When I

C mode is selected, D2, D1 should be tied together and serve as SDA

out

SDA

in application and D0 is the serial clock input, SCL.

FR O This pin outputs RAM write synchronization signa

l. Proper timing between MCU

data writing and frame display timing can be achieved to prevent tearing effect.

It should be kept NC if it is not used.

T0 I/O This is a reserved pin. It should be kept NC.

T1 I/O This is a reserved pin. It should be kept NC.

SEG0 ~

SEG127

O These pins provide the OLED segment driving signals. These pins are V

state when

display is OFF.

COM0 ~

COM95

These pins provide the Common switch signals to the OLED panel. These pins are in

high impedance state when display is OFF.

TR[10:0] - Reserved pin. It should be kept NC.

NC - This is dummy pin. It should be kept NC.

SSD1317

Rev 1.0

P 11/32

Dec 2015

Solomon Systech

6 FUNCTIONAL BLOCK DESCRIPTIONS

6.1 MCU Interface selection

SSD1317 MCU interface consist of 8 data pins and 5 control pins. The pin assignment at different interface

mode is summarized in Table 6-1. Different MCU mode can be set by hardware selection on BS[2:0] pins

(please refer to

Table 5-2

for BS[2:0] setting).

Table 6-1 : MCU interface assignment under different bus interface mode

Pin Name

Bus

Interface

Data/Command Interface Control Signal

D7 D6 D5 D4 D3 D2 D1 D0 E R/W#

CS#

D/C# RES#

8-bit 8080 D[7:0] RD#

WR# CS#

D/C# RES#

8-bit 6800 D[7:0] E R/W#

CS#

D/C# RES#

3-wire SPI Tie LOW SDIN

SCLK

Tie LOW CS#

Tie LOW

RES#

4-wire SPI Tie LOW SDIN

SCLK

Tie LOW CS#

D/C# RES#

C Tie LOW SDA

OUT

SDA

SCL Tie LOW SA0 RES#

6.1.1 MCU Parallel 6800-series Interface

The parallel interface consists of 8 bi-directional data pins (

D[7:0]

), R/W#, D/C#, E and CS#.

A LOW in R/W# indicates WRITE operation and HIGH in R/W# indicates READ operation.

A LOW in D/C# indicates COMMAND read/write and HIGH in D/C# indicates DATA read/write.

The E input serves as data latch signal while CS# is LOW. Data is latched at the falling edge of E signal.

Table 6-2 : Control pins of 6800 interface

Function E R/W#

CS# D/C#

Write command

↓ L L L

Read status ↓ H L L

Write data ↓ L L H

Read data ↓ H L H

Note

(1)

↓ stands for falling edge of signal

H stands for HIGH in signal

L stands for LOW in signal

In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline

processing is internally performed which requires the insertion of a dummy read before the first actual display

data read. This is shown in Figure 6-1.

Solomon Systech

Dec 2015

P 12/32

Rev 1.0

SSD1317

Figure 6-1 : Data read back procedure - insertion of dummy read

N n n+1 n+2

R/W#

Databus

Write column

address

Read 1st dataDummy read Read 2nd data Read 3rd data

6.1.2 MCU Parallel 8080-series Interface

The parallel interface consists of 8 bi-directional data pins (D[7:0]), RD#, WR#, D/C# and CS#.

A LOW in D/C# indicates COMMAND read/write and HIGH in D/C# indicates DATA read/write.

A rising edge of RD# input serves as a data READ latch signal while CS# is kept LOW.

A rising edge of WR# input serves as a data/command WRITE latch signal while CS# is kept LOW.

Figure 6-2 : Example of Write procedure in 8080 parallel interface mode

CS#

WR#

D[7:0]

D/C#

RD#

high

low

Figure 6-3 : Example of Read procedure in 8080 parallel interface mode

CS#

WR#

D[7:0]

D/C#

RD#

high

low

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