TMS320x2806x Piccolo DSP技术参考手册：系统控制与特性详解

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TMS320x2806x Piccolo Technical Reference Manual是一份详细的技术手册，由TI（Texas Instruments）针对其DSP（数字信号处理器）芯片TMS320x28069编写。该文档发布于2011年1月并经过2019年11月的修订，提供了对处理器系统控制、中断管理、存储器管理、代码安全模块(CSM)、时钟管理、GPIO（通用输入/输出）等核心功能的深入介绍。 1. **系统控制与中断管理**：这部分阐述了处理器如何处理系统的启动、配置以及中断事件，确保了程序的正常执行和响应外部事件的能力。 2. **Flash与OTP内存**：Flash用于长期存储程序代码，具有非易失性特性；OTP（一次性编程）内存则用于存放固定的配置数据，如跳线设置，不可修改。 3. **Flash和OTP的工作模式与寄存器**：指南解释了不同工作模式下的内存管理和操作，并列出了相关的控制寄存器，以便用户理解和优化功耗。 4. **代码安全模块(CSM)**：CSM是关键的安全特性，用于保护硬件免受未授权访问。它包括功能描述、对其他芯片资源的影响、在用户应用中的集成方法，以及保护措施和功能总结。 5. **时钟管理**：涉及时钟系统和系统控制的交互，包括主时钟振荡器(OSC)、锁相环路(PLL)以及低功耗模式下的时钟配置，还涵盖了CPU Watchdog定时器。 6. **32位CPU定时器**：三个独立的定时器被详细介绍，它们在各种应用场景中提供精确的时间测量和定时功能。 7. **GPIO模块**：这是处理器对外部设备通信的核心部分，包括模块概述、配置选项、输入处理以及与外设接口的兼容性。通过阅读这份技术参考手册，开发人员可以深入了解TMS320x28069的特性和用法，从而优化他们的设计，确保高性能、可靠性和安全性。对于从事嵌入式系统设计或DSP应用开发的工程师来说，这是不可或缺的参考资料。

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SPRUH18H–January 2011–Revised November 2019

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List of Figures

3-11. Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up On Synchronization Event........ 261

3-12. Counter-Compare Submodule .......................................................................................... 261

3-13. Detailed View of the Counter-Compare Submodule ................................................................. 263

3-14. Counter-Compare Event Waveforms in Up-Count Mode............................................................ 265

3-15. Counter-Compare Events in Down-Count Mode ..................................................................... 266

3-16. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down On

Synchronization Event ................................................................................................... 267

3-17. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up On Synchronization

Event ....................................................................................................................... 267

3-18. Action-Qualifier Submodule ............................................................................................. 268

3-19. Action-Qualifier Submodule Inputs and Outputs...................................................................... 269

3-20. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs ........................................... 270

3-21. Up-Down-Count Mode Symmetrical Waveform....................................................................... 273

3-22. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and

EPWMxB—Active High .................................................................................................. 274

3-23. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and

EPWMxB—Active Low ................................................................................................... 276

3-24. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA............. 277

3-25. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and

EPWMxB — Active Low ................................................................................................. 279

3-26. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and

EPWMxB — Complementary ........................................................................................... 280

3-27. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active

Low ......................................................................................................................... 281

3-28. Dead-Band Submodule .................................................................................................. 282

3-29. Configuration Options for the Dead-Band Submodule............................................................... 283

3-30. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%) ................................................... 285

3-31. PWM-Chopper Submodule .............................................................................................. 287

3-32. PWM-Chopper Submodule Operational Details ...................................................................... 288

3-33. Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only ................................ 288

3-34. PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses ....... 289

3-35. PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining

Pulses ...................................................................................................................... 290

3-36. Trip-Zone Submodule .................................................................................................... 291

3-37. Trip-Zone Submodule Mode Control Logic............................................................................ 295

3-38. Trip-Zone Submodule Interrupt Logic .................................................................................. 296

3-39. Event-Trigger Submodule ............................................................................................... 297

3-40. Event-Trigger Submodule Inter-Connectivity of ADC Start of Conversion ........................................ 297

3-41. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs ........................................ 298

3-42. Event-Trigger Interrupt Generator ...................................................................................... 299

3-43. Event-Trigger SOCA Pulse Generator ................................................................................. 300

3-44. Event-Trigger SOCB Pulse Generator ................................................................................. 300

3-45. Digital-Compare Submodule High-Level Block Diagram ............................................................ 301

3-46. DCAEVT1 Event Triggering ............................................................................................. 303

3-47. DCAEVT2 Event Triggering ............................................................................................. 303

3-48. DCBEVT1 Event Triggering ............................................................................................. 304

3-49. DCBEVT2 Event Triggering ............................................................................................. 304

3-50. Event Filtering ............................................................................................................. 305

3-51. Blanking Window Timing Diagram...................................................................................... 306

3-52. Simplified ePWM Module ................................................................................................ 307

3-53. EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave ...................................... 308

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SPRUH18H–January 2011–Revised November 2019

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List of Figures

3-54. Control of Four Buck Stages. Here F

PWM1

≠ F

PWM2

≠ F

PWM3

≠ F

PWM4

.................................................... 309

3-55. Buck Waveforms for (Note: Only three bucks shown here)......................................................... 310

3-56. Control of Four Buck Stages. (Note: F

PWM2

= N x F

PWM1

) ............................................................. 312

3-57. Buck Waveforms for (Note: F

PWM2

= F

PWM1)

) ............................................................................ 313

3-58. Control of Two Half-H Bridge Stages (F

PWM2

= N x F

PWM1

) ........................................................... 315

3-59. Half-H Bridge Waveforms for (Note: Here F

PWM2

= F

PWM1

) ........................................................... 316

3-60. Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control............................... 318

3-61. 3-Phase Inverter Waveforms for (Only One Inverter Shown)....................................................... 319

3-62. Configuring Two PWM Modules for Phase Control .................................................................. 321

3-63. Timing Waveforms Associated With Phase Control Between 2 Modules ......................................... 322

3-64. Control of a 3-Phase Interleaved DC/DC Converter ................................................................. 323

3-65. 3-Phase Interleaved DC/DC Converter Waveforms for ............................................................. 324

3-66. Controlling a Full-H Bridge Stage (F

PWM2

= F

PWM1)

.................................................................... 327

3-67. ZVS Full-H Bridge Waveforms .......................................................................................... 328

3-68. Peak Current Mode Control of a Buck Converter .................................................................... 330

3-69. Peak Current Mode Control Waveforms for .......................................................................... 330

3-70. Control of Two Resonant Converter Stages .......................................................................... 332

3-71. H-Bridge LLC Resonant Converter PWM Waveforms ............................................................... 332

3-72. Time-Base Period Register (TBPRD) .................................................................................. 334

3-73. Time Base Period High Resolution Register (TBPRDHR) .......................................................... 334

3-74. Time Base Period Mirror Register (TBPRDM) ........................................................................ 334

3-75. Time-Base Period High Resolution Mirror Register (TBPRDHRM) ............................................... 335

3-76. Time-Base Phase Register (TBPHS) .................................................................................. 335

3-77. Time-Base Phase High Resolution Register (TBPHSHR)........................................................... 336

3-78. Time-Base Counter Register (TBCTR) ................................................................................ 336

3-79. Time-Base Control Register (TBCTL).................................................................................. 336

3-80. Time-Base Status Register (TBSTS)................................................................................... 339

3-81. EPWM DMA/CLA Configuration (EPWMCFG) Register............................................................. 339

3-82. High Resolution Period Control Register (HRPCTL)................................................................. 339

3-83. Counter-Compare A Register (CMPA) ................................................................................ 341

3-84. Counter-Compare B Register (CMPB)................................................................................. 341

3-85. Counter-Compare Control Register (CMPCTL)....................................................................... 343

3-86. Compare A High Resolution Register (CMPAHR) ................................................................... 344

3-87. Counter-Compare A Mirror Register (CMPAM) ...................................................................... 344

3-88. Compare A High Resolution Mirror Register .......................................................................... 344

3-89. Action-Qualifier Output A Control Register (AQCTLA)............................................................... 345

3-90. Action-Qualifier Output B Control Register (AQCTLB)............................................................... 346

3-91. Action-Qualifier Software Force Register (AQSFRC) ................................................................ 347

3-92. Action-Qualifier Continuous Software Force Register (AQCSFRC)................................................ 348

3-93. Dead-Band Generator Control Register (DBCTL).................................................................... 349

3-94. Dead-Band Generator Rising Edge Delay Register (DBRED)...................................................... 350

3-95. Dead-Band Generator Falling Edge Delay Register (DBFED) ..................................................... 350

3-96. PWM-Chopper Control Register (PCCTL)............................................................................. 351

3-97. Trip-Zone Select Register (TZSEL) .................................................................................... 353

3-98. Trip-Zone Control Register (TZCTL) ................................................................................... 354

3-99. Trip-Zone Enable Interrupt Register (TZEINT)........................................................................ 355

3-100. Trip-Zone Flag Register (TZFLG)....................................................................................... 356

3-101. Trip-Zone Clear Register (TZCLR) ..................................................................................... 357

3-102. Trip-Zone Force Register (TZFRC)..................................................................................... 357

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SPRUH18H–January 2011–Revised November 2019

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List of Figures

3-103. Trip Zone Digital Compare Event Select Register (TZDCSEL)..................................................... 358

3-104. Digital Compare Trip Select (DCTRIPSEL) ........................................................................... 360

3-105. Digital Compare A Control Register (DCACTL) ...................................................................... 361

3-106. Digital Compare B Control Register (DCBCTL)....................................................................... 362

3-107. Digital Compare Filter Control Register (DCFCTL) .................................................................. 362

3-108. Digital Compare Capture Control Register (DCCAPCTL) ........................................................... 363

3-109. Digital Compare Counter Capture Register (DCCAP) ............................................................... 363

3-110. Digital Compare Filter Offset Register (DCFOFFSET) .............................................................. 364

3-111. Digital Compare Filter Offset Counter Register (DCFOFFSETCNT) .............................................. 364

3-112. Digital Compare Filter Window Register (DCFWINDOW)........................................................... 365

3-113. Digital Compare Filter Window Counter Register (DCFWINDOWCNT)........................................... 365

3-114. Event-Trigger Selection Register (ETSEL) ............................................................................ 365

3-115. Event-Trigger Prescale Register (ETPS) .............................................................................. 367

3-116. Event-Trigger Flag Register (ETFLG).................................................................................. 368

3-117. Event-Trigger Clear Register (ETCLR) ................................................................................ 369

3-118. Event-Trigger Force Register (ETFRC)................................................................................ 369

4-1. Resolution Calculations for Conventionally Generated PWM....................................................... 373

4-2. Operating Logic Using MEP............................................................................................. 375

4-3. HRPWM Extension Registers and Memory Configuration .......................................................... 376

4-4. HRPWM System Interface............................................................................................... 377

4-5. HRPWM Block Diagram ................................................................................................. 378

4-6. Required PWM Waveform for a Requested Duty = 30.0% ......................................................... 380

4-7. Low % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0)............................................. 383

4-8. High % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0) ........................................... 385

4-9. Up-Count Duty Cycle Range Limitation Example (HRPCTL[HRPE]=1)........................................... 385

4-10. Up-Down Count Duty Cycle Range Limitation Example (HRPCTL[HRPE]=1) ................................... 386

4-11. Simple Buck Controlled Converter Using a Single PWM............................................................ 390

4-12. PWM Waveform Generated for Simple Buck Controlled Converter ............................................... 390

4-13. Simple Reconstruction Filter for a PWM Based DAC................................................................ 392

4-14. PWM Waveform Generated for the PWM DAC Function ........................................................... 392

4-15. HRPWM Configuration Register (HRCNFG) .......................................................................... 396

4-16. Counter Compare A High Resolution Register (CMPAHR) ......................................................... 397

4-17. TB Phase High Resolution Register (TBPHSHR) .................................................................... 397

4-18. Time Base Period High Resolution Register .......................................................................... 397

4-19. Compare A High Resolution Mirror Register .......................................................................... 398

4-20. Time-Base Period High Resolution Mirror Register .................................................................. 398

4-21. High Resolution Period Control Register (HRPCTL)................................................................. 398

4-22. High Resolution Micro Step Register (HRMSTEP) (EALLOW protected): ........................................ 399

5-1. HRCAP Module System Block Diagram ............................................................................... 405

5-2. HRCAP Block Diagram .................................................................................................. 406

5-3. HCCAPCLK Generation ................................................................................................. 407

5-4. HCCOUNTER Behavior During High Pulse Width Capture......................................................... 407

5-5. Rise vs. Fall Capture Events ............................................................................................ 408

5-6. High Pulse Width Normal Mode Capture .............................................................................. 409

5-7. Low Pulse Width Normal Mode Capture............................................................................... 409

5-8. HRCAP High-Resolution Mode Operating Logic ..................................................................... 410

5-9. Interrupts in HRCAP Module ............................................................................................ 411

5-10. HRCAP Control Register (HCCTL) .................................................................................... 412

5-11. HRCAP Interrupt Flag Register (HCIFR) .............................................................................. 412

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SPRUH18H–January 2011–Revised November 2019

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List of Figures

5-12. HRCAP Interrupt Clear Register (HCICLR) ........................................................................... 414

5-13. HRCAP Interrupt Force Register (HCIFRC) .......................................................................... 415

5-14. HRCAP Counter Register (HCCOUNTER)............................................................................ 415

5-15. HRCAP Capture Counter On Rising Edge 0 Register (HCCAPCNTRISE0)...................................... 416

5-16. HRCAP Capture Counter On Rising Edge 1 Register (HCCAPCNTRISE1)...................................... 416

5-17. HRCAP Capture Counter On Falling Edge 0 Register (HCCAPCNTFALL0) ..................................... 416

5-18. HRCAP Capture Counter On Falling Edge 1 Register (HCCAPCNTFALL1) ..................................... 417

5-19. LowPulseWidth0 Capture on RISE and FALL Events ............................................................... 419

5-20. HighPulseWidth0/1 Capture on RISE and FALL Events ............................................................ 420

5-21. PeriodWidthRise0 and PeriodWidthFall0 Capture on RISE and FALL Events ................................... 421

6-1. Multiple eCAP Modules In A C28x System............................................................................ 427

6-2. Capture and APWM Modes of Operation.............................................................................. 428

6-3. Counter Compare and PRD Effects on the eCAP Output in APWM Mode ....................................... 429

6-4. eCAP Block Diagram..................................................................................................... 430

6-5. Event Prescale Control................................................................................................... 431

6-6. Prescale Function Waveforms .......................................................................................... 431

6-7. Details of the Continuous/One-shot Block............................................................................. 432

6-8. Details of the Counter and Synchronization Block ................................................................... 433

6-9. Interrupts in eCAP Module .............................................................................................. 435

6-10. PWM Waveform Details Of APWM Mode Operation ................................................................ 436

6-11. Time-Base Frequency and Period Calculation........................................................................ 437

6-12. Capture Sequence for Absolute Time-stamp and Rising Edge Detect ............................................ 437

6-13. Capture Sequence for Absolute Time-stamp With Rising and Falling Edge Detect ............................. 438

6-14. Capture Sequence for Delta Mode Time-stamp and Rising Edge Detect......................................... 439

6-15. Capture Sequence for Delta Mode Time-stamp With Rising and Falling Edge Detect.......................... 440

6-16. PWM Waveform Details of APWM Mode Operation ................................................................. 441

6-17. TSCTR Register .......................................................................................................... 444

6-18. CTRPHS Register ........................................................................................................ 445

6-19. CAP1 Register ............................................................................................................ 446

6-20. CAP2 Register ............................................................................................................ 447

6-21. CAP3 Register ............................................................................................................ 448

6-22. CAP4 Register ............................................................................................................ 449

6-23. ECCTL1 Register ......................................................................................................... 450

6-24. ECCTL2 Register ......................................................................................................... 452

6-25. ECEINT Register.......................................................................................................... 454

6-26. ECFLG Register .......................................................................................................... 456

6-27. ECCLR Register .......................................................................................................... 458

6-28. ECFRC Register .......................................................................................................... 459

7-1. Optical Encoder Disk ..................................................................................................... 461

7-2. QEP Encoder Output Signal for Forward/Reverse Movement...................................................... 461

7-3. Index Pulse Example..................................................................................................... 462

7-4. Functional Block Diagram of the eQEP Peripheral................................................................... 464

7-5. Functional Block Diagram of Decoder Unit............................................................................ 466

7-6. Quadrature Decoder State Machine.................................................................................... 467

7-7. Quadrature-clock and Direction Decoding............................................................................. 468

7-8. Position Counter Reset by Index Pulse for 1000 Line Encoder (QPOSMAX = 3999 or 0xF9F) ............... 470

7-9. Position Counter Underflow/Overflow (QPOSMAX = 4) ............................................................ 471

7-10. Software Index Marker for 1000-line Encoder (QEPCTL[IEL] = 1)................................................. 472

7-11. Strobe Event Latch (QEPCTL[SEL] = 1)............................................................................... 473

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SPRUH18H–January 2011–Revised November 2019

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List of Figures

7-12. eQEP Position-compare Unit............................................................................................ 474

7-13. eQEP Position-compare Event Generation Points ................................................................... 475

7-14. eQEP Position-compare Sync Output Pulse Stretcher .............................................................. 475

7-15. eQEP Edge Capture Unit ................................................................................................ 477

7-16. Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010) .................................. 477

7-17. eQEP Edge Capture Unit - Timing Details ............................................................................ 478

7-18. eQEP Watchdog Timer .................................................................................................. 479

7-19. eQEP Unit Time Base.................................................................................................... 480

7-20. EQEP Interrupt Generation.............................................................................................. 480

7-21. QPOSCNT Register ...................................................................................................... 484

7-22. QPOSINIT Register....................................................................................................... 485

7-23. QPOSMAX Register...................................................................................................... 486

7-24. QPOSCMP Register...................................................................................................... 487

7-25. QPOSILAT Register...................................................................................................... 488

7-26. QPOSSLAT Register..................................................................................................... 489

7-27. QPOSLAT Register....................................................................................................... 490

7-28. QUTMR Register.......................................................................................................... 491

7-29. QUPRD Register.......................................................................................................... 492

7-30. QWDTMR Register ....................................................................................................... 493

7-31. QWDPRD Register ....................................................................................................... 494

7-32. QDECCTL Register....................................................................................................... 495

7-33. QEPCTL Register......................................................................................................... 497

7-34. QCAPCTL Register....................................................................................................... 500

7-35. QPOSCTL Register....................................................................................................... 501

7-36. QEINT Register ........................................................................................................... 502

7-37. QFLG Register ............................................................................................................ 504

7-38. QCLR Register............................................................................................................ 506

7-39. QFRC Register............................................................................................................ 508

7-40. QEPSTS Register ........................................................................................................ 510

7-41. QCTMR Register.......................................................................................................... 512

7-42. QCPRD Register.......................................................................................................... 513

7-43. QCTMRLAT Register..................................................................................................... 514

7-44. QCPRDLAT Register..................................................................................................... 515

8-1. ADC Block Diagram ...................................................................................................... 518

8-2. SOC Block Diagram ...................................................................................................... 519

8-3. ADCINx Input Model...................................................................................................... 520

8-4. ONESHOT Single Conversion .......................................................................................... 525

8-5. Round Robin Priority Example .......................................................................................... 527

8-6. High Priority Example .................................................................................................... 528

8-7. Interrupt Structure ........................................................................................................ 530

8-8. ADC Control Register 1 (ADCCTL1) (Address Offset 00h) ......................................................... 534

8-9. ADC Control Register 2 (ADCCTL2) (Address Offset 01h) ........................................................ 536

8-10. ADC Interrupt Flag Register (ADCINTFLG) (Address Offset 04h) ................................................. 537

8-11. ADC Interrupt Flag Clear Register (ADCINTFLGCLR) (Address Offset 05h) .................................... 538

8-12. ADC Interrupt Overflow Register (ADCINTOVF) (Address Offset 06h) ........................................... 538

8-13. ADC Interrupt Overflow Clear Register (ADCINTOVFCLR) (Address Offset 07h)............................... 538

8-14. Interrupt Select 1 And 2 Register (INTSEL1N2) (Address Offset 08h) ............................................ 539

8-15. Interrupt Select 3 And 4 Register (INTSEL3N4) (Address Offset 09h) ............................................ 539

8-16. Interrupt Select 5 And 6 Register (INTSEL5N6) (Address Offset 0Ah)............................................ 539

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