VHDL语法详解：IEEE Std 1076-2008标准

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"VHDL语法IEEE std 1076-2008是针对FPGA设计初学者的一份重要参考资料，涵盖了VHDL的基本结构、声明、库引用和数据类型的详细说明。此标准由IEEE Computer Society的Design Automation Standards Committee赞助，并在2009年进行了修订。" VHDL（Very High Speed Integrated Circuit Hardware Description Language）是一种广泛用于数字逻辑系统设计的语言，特别是在FPGA（Field-Programmable Gate Array）领域。IEEE Std 1076-2008是VHDL的官方标准，它定义了语言的规范和语法，为设计者提供了可靠的参考。 1. **结构体（Structures）**：在VHDL中，结构体用于描述硬件系统的物理组织。它包括实体（Entity）、架构（Architecture）和配置（Configuration）。实体描述了系统接口，而架构则定义了系统内部的行为和连接。配置则允许对设计进行实例化和绑定。 2. **声明（Declarations）**：声明部分是VHDLDesign的重要组成部分，用于定义信号（Signals）、变量（Variables）、常量（Constants）、类型（Types）和实体等。声明有助于明确设计中的各种元素及其属性。 3. **库调用（Library Calls）**：VHDL库包含了预定义的数据类型、组件和包，通过库调用，设计师可以使用这些预定义的元素。例如，`ieee`库是最常用的库，包含了基本的逻辑操作符和数据类型。 4. **数据类型（Data Types）**：VHDL提供了丰富的数据类型，包括基本类型（如BIT、BOOLEAN、INTEGER、REAL等）、数组类型、记录类型、枚举类型等。设计师可以根据需求定义自己的数据类型，以满足特定设计的要求。 5. **进程（Processes）**：进程是VHDL中描述并行行为的关键构造，类似于软件编程中的循环或条件语句。它们可以处理时序逻辑，是异步电路建模的核心。 6. **组件（Components）**：组件是已声明的设计单元，可以在其他设计中作为模块化组件进行复用。通过组件实例化，设计师可以将复杂的系统分解为更小、更易管理的部分。 7. **仿真与综合（Synthesis）**：VHDL代码既可以进行仿真验证，也可以被综合工具转换为可实现的逻辑门级表示，适用于FPGA或ASIC的实现。 8. **包（Packages）**：包是用来组织和重用代码的机制，包含类型定义、常量、函数和过程。通过创建自定义包，设计师可以定义特定领域的专用功能。理解并掌握VHDL IEEE Std 1076-2008标准对于FPGA设计至关重要，它可以帮助初学者构建坚实的基础，进一步深入学习数字系统设计的高级概念。这份标准文档详细阐述了语言的各个方面，是任何VHDL学习者的必备参考资料。

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IEEE STANDARD VHDL LANGUAGE REFERENCE MANUAL Std 1076-2008

f) Braces { } enclose a repeated item or items on the right-hand side of a production. The items may

appear zero or more times; the repetitions occur from left to right as with an equivalent left-recursive

rule. Thus, the following two productions are equivalent:

term ::= factor { multiplying_operator factor }

term ::= factor | term multiplying_operator factor

g) If the name of any syntactic category starts with an italicized part, it is equivalent to the category

name without the italicized part. The italicized part is intended to convey some semantic informa-

tion. For example, type_name and subtype_name are both syntactically equivalent to name alone.

h) The term simple_name is used for any occurrence of an identifier that already denotes some

declared entity.

1.3.3 Semantic description

The meaning and restrictions of a particular construct are described with a set of narrative rules immediately

following the syntactic productions. In these rules, an italicized term indicates the definition of that term,

and identifiers appearing entirely in uppercase letters refer to definitions in package STANDARD (see

16.3).

The following terms are used in these semantic descriptions with the following meanings:

erroneous: The condition described represents an ill-formed description; however, implementations are not

required to detect and report this condition. Conditions are deemed erroneous only when it is impossible in

general to detect the condition during the processing of the language.

error: The condition described represents an ill-formed description; implementations are required to detect

the condition and report an error to the user of the tool.

illegal: A synonym for “error.”

legal: The condition described represents a well-formed description.

1.3.4 Front matter, examples, notes, references, and annexes

Prior to this subclause are several pieces of introductory material; following Clause 24 are some annexes and

an index. The front matter, annexes (except Annex B), and index serve to orient and otherwise aid the user

of this standard, but are not part of the definition of VHDL; Annex B, however, is normative.

Some clauses of this standard contain examples, notes, and cross-references to other clauses of the standard;

these parts always appear at the end of a clause. Examples are meant to illustrate the possible forms of the

construct described. Illegal examples are italicized. Notes are meant to emphasize consequences of the rules

described in the clause or elsewhere. In order to distinguish notes from the other narrative portions of this

standard, notes are set as enumerated paragraphs in a font smaller than the rest of the text. Cross-references

are meant to guide the user to other relevant clauses of the standard. Examples, notes, and cross-references

are not part of the definition of the language.

1.3.5 Incorporation of Property Specification Language

VHDL incorporates the simple subset of the Property Specification Language (PSL) as an embedded

language for formal specification of the behavior of a VHDL description. PSL is defined by

IEEE Std 1850

-2005.

All PSL constructs that appear in a VHDL description shall conform to the

Information on references can be found in Clause 2.

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IEEE STANDARD VHDL LANGUAGE REFERENCE MANUAL Std 1076-2008

2. Normative references

The following referenced documents are indispensable for the application of this document (i.e., they must

be understood and used, so each referenced document is cited in text and its relationship to this document is

explained). For dated references, only the edition cited applies. For undated references, the latest edition of

the referenced document (including any amendments or corrigenda) applies.

IEEE Std 754

-1985 (Reaff 1990), IEEE Standard for Binary Floating-Point Arithmetic.

IEEE Std 854

-1987 (Reaff 1994), IEEE Standard for Radix-Independent Floating-Point Arithmetic.

IEEE Std 1850

-2005, IEEE Standard for Property Specification Language (PSL).

ISO/IEC 8859-1:1998, Information technology—8-bit single-byte coded graphic character sets—Part 1:

Latin alphabet No. 1.

ISO/IEC 9899:1999, Programming languages—C.

ISO/IEC 9899:1999/Cor 1:2001, Programming languages—C, Technical Corrigendum 1.

ISO/IEC 9899:1999/Cor 2:2004, Programming languages—C, Technical Corrigendum 2.

ISO/IEC 19501:2005, Information technology—Open Distributed Processing—Unified Modeling Language

(UML) Version 1.4.2.

IEEE publications are available from the Institute of Electrical and Electronics Engineers, 445 Hoes Lane, P.O. Box 1331, Piscataway,

NJ 08855-1331, USA (http://standards.ieee.org/).

The IEEE standards or products referred to in this clause are trademarks of the Institute of Electrical and Electronics Engineers, Inc.

ISO/IEC publications are available from the ISO Central Secretariat, Case Postale 56, 1 rue de Varembé, CH-1211, Genève 20, Swit-

zerland/Suisse (http://www.iso.ch/). ISO/IEC publications are also available in the United States from Global Engineering Documents,

15 Inverness Way East, Englewood, Colorado 80112, USA (http://global.ihs.com/). Electronic copies are available in the United States

from the American National Standards Institute, 25 West 43rd Street, 4th Floor, New York, NY 10036, USA (http://www.ansi.org/).

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IEEE STANDARD VHDL LANGUAGE REFERENCE MANUAL Std 1076-2008

3. Design entities and configurations

3.1 General

The design entity is the primary hardware abstraction in VHDL. It represents a portion of a hardware design

that has well-defined inputs and outputs and performs a well-defined function. A design entity may

represent an entire system, a subsystem, a board, a chip, a macro-cell, a logic gate, or any level of abstraction

in-between. A configuration can be used to describe how design entities are put together to form a complete

design.

A design entity may be described in terms of a hierarchy of blocks, each of which represents a portion of the

whole design. The top-level block in such a hierarchy is the design entity itself; such a block is an external

block that resides in a library and may be used as a component of other designs. Nested blocks in the

hierarchy are internal blocks, defined by block statements (see 11.2).

A design entity may also be described in terms of interconnected components. Each component of a design

entity may be bound to a lower-level design entity in order to define the structure or behavior of that

component. Successive decomposition of a design entity into components, and binding those components to

other design entities that may be decomposed in like manner, results in a hierarchy of design entities

representing a complete design. Such a collection of design entities is called a design hierarchy. The

bindings necessary to identify a design hierarchy can be specified in a configuration of the top-level entity in

the hierarchy.

This clause describes the way in which design entities and configurations are defined. A design entity is

defined by an entity declaration together with a corresponding architecture body. A configuration is defined

by a configuration declaration.

3.2 Entity declarations

3.2.1 General

An entity declaration defines the interface between a given design entity and the environment in which it is

used. It may also specify declarations and statements that are part of the design entity. A given entity

declaration may be shared by many design entities, each of which has a different architecture. Thus, an

entity declaration can potentially represent a class of design entities, each with the same interface.

entity_declaration ::=

entity identifier is

entity_header

entity_declarative_part

[ begin

entity_statement_part ]

end [ entity ] [ entity_simple_name ] ;

The entity header and entity declarative part consist of declarative items that pertain to each design entity

whose interface is defined by the entity declaration. The entity statement part, if present, consists of

concurrent statements that are present in each such design entity.

If a simple name appears at the end of an entity declaration, it shall repeat the identifier of the entity

declaration.

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