MAX96717: GMSL视频串行器与双向控制通道的高速解决方案

需积分: 5 88 浏览量更新于2024-06-15 收藏 2.38MB PDF 举报

MAX96717是一款专为汽车电子应用设计的高性能GMSL（Global Mobile Satellite Link） serializer/deserializer (串行器/解串器)。它在汽车信息娱乐系统中发挥关键作用，负责将视频信号从MII/CSI-2接口接收，并通过GMSL 2线性链路进行传输，同时处理双向控制通道数据。这款设备支持两种数据传输速率，3Gbps的前向传输和187.5Mbps的反向传输，以满足不同的通信需求。该芯片采用本地I2C/UART接口进行编程，或者可以通过链路与匹配的deserializer进行交互。集成的特性包括两个I2C/UART通道，灵活的GPIO，SPI隧道，一个内置的ADC（模拟到数字转换器），温度传感器以及一套全面的功能安全诊断系统。MAX96717的工作范围广泛，可在-40°C至+105°C的恶劣环境下稳定运行，并且符合AEC-Q100 Grade 2等级，确保在严苛的汽车环境中的可靠性和耐用性。 GMSL 2技术允许数据在低成本的50Ω同轴电缆或100Ω屏蔽双绞线（STP）上传输，这些电缆需符合GMSL 2规范。用户应参考表格1获取关于常用汽车电缆典型最大长度的指导，实际使用时需注意信号衰减的影响。在选择电缆时，请务必咨询制造商获取最新的GMSL 2电缆规格信息，以确保最佳的信号质量和传输距离。 MAX96717是一款在汽车通信领域不可或缺的解决方案，它不仅提供了高速的数据传输能力，还注重了可靠性、稳定性以及与各种接口的兼容性，为现代汽车电子系统的设计提供了强大而灵活的支持。

Electrical Characteristics (continued)

DD18

= 1.7V to 1.9V, V

= 0.95V to 1.26V, V

DDIO

= 1.7V to 3.6V, T

= -40°C to +105°C, EP connected to PCB ground, typical

values are at V

DD18

= V

DDIO

= 1.8V, V

= 1.0V, T

= +25°C, unless otherwise noted. (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

GPI-GPO Skew

Reverse Path

SKEW

Delay compensated mode. 7 ns

AC ELECTRICAL CHARACTERISTICS / D-PHY HS RECEIVER

Common-Mode

Interference Beyond

450MHz

ΔV

CMRX(HF)

Note 2, Note 5,

Note 8

Data rate >

1.5Gbps

50 mV

Common-Mode

Interference

50MHz–450MHz

ΔV

CMRX(LF)

Note 2, Note 5,

Note 6

Data rate >

1.5Gbps

-25 25 mV

Common-Mode

Reflection Coefficient

Scc

450MHz < f < 1.875GHz -5 dB

Differential-Mode

Reflection Coefficient

Sdd

f < 20MHz -22.5

dB f = 1.25GHz -12

f = 1.875GHz -9.7

AC ELECTRICAL CHARACTERISTICS / D-PHY LP RECEIVER—SEE Figure 5 (Note 2)

Input Pulse Rejection e

SPIKE

See Figure 5 300 V

Minimum Pulse Width

Response

MIN-RX

See Figure 5 20 ns

Peak Interference

Amplitude

INT

200 mV

Interference Frequency f

INT

450 MHz

AC ELECTRICAL CHARACTERISTICS / D-PHY DATA CLOCK TIMING—SEE Figure 6 (Note 2)

UI Instantaneous UI

INST

0.4 12.5 ns

UI Variation ΔUI

UI ≥ 1ns, within a single burst -10% +10%

0.667ns < UI < 1ns, within a single burst -5% 5%

Data to Clock Setup

Time

SETUP[RX]

< 1.0Gbps 0.15

INST

> 1.0Gbps 0.2

Data to Clock Hold Time t

HOLD[RX]

< 1.0Gbps 0.15

INST

> 1.0Gbps 0.2

Static Data to Clock

Skew

SKEW[RX]

static

> 1.5Gbps -0.2 0.2 UI

INST

Dynamic Data to Clock

Skew Window Rx

Tolerance

SETUP[RX]

HOLD[RX]

Dynamic

> 1.5Gbps 0.50 UI

INST

AC ELECTRICAL CHARACTERISTICS / D-PHY GLOBAL OPERATION TIMING (Note 2)

Time Interval When the

HS Receiver Ignores

Any Clock Lane HS

Transitions, Starting

from the Beginning of

CLK-PREPARE

CLK-SETTLE

See Figure 9 95 300 ns

MAX96717 CSI-2 to GMSL2 Serializer

www.analog.com Analog Devices | 16

Electrical Characteristics (continued)

DD18

= 1.7V to 1.9V, V

= 0.95V to 1.26V, V

DDIO

= 1.7V to 3.6V, T

= -40°C to +105°C, EP connected to PCB ground, typical

values are at V

DD18

= V

DDIO

= 1.8V, V

= 1.0V, T

= +25°C, unless otherwise noted. (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

MOSI Input Setup Time t

SIS

Before SCLK rising edge (Note 2) 5 ns

MOSI Input Hold Time t

SIH

After SCLK rising edge (Note 2) 3 ns

AC ELECTRICAL CHARACTERISTICS / MONITOR ADC

Conversion Time 430 μs

ADC Setup Time

T_ADC_SETU

ADC ready after power-up enable.

Excluding external V

REF

power-up time.

30 μs

ADC Clock f

ADCCLK

2.5 MHz

AC ELECTRICAL CHARACTERISTICS / REFERENCE CLOCK INPUT REQUIREMENTS (CRYSTAL) (X1,X2) (Note 2)

Frequency Fundamental mode only 25 MHz

Frequency Stability +

Frequency Tolerance

±200 ppm

AC ELECTRICAL CHARACTERISTICS / REFERENCE CLOCK REQUIREMENTS (EXTERNAL CLOCK INPUT ON X1, X2

FLOATING) (Note 2)

Frequency f

REF

25 MHz

Frequency Stability +

Frequency Tolerance

±200 ppm

Input Jitter t

JIN

6Gbps/187.5Mbps, sinusoidal jitter <

1MHz (rising edge), downstream

deserializer using crystal reference

600 ps (p-p)

Duty Cycle T

DUTY

40 60 %

Maximum Rise Time t

10% to 90% 5 ns

Maximum Fall Time t

80% to 20% 4 ns

AC ELECTRICAL CHARACTERISTICS / REFERENCE CLOCK OUTPUT (RCLKOUT)

Frequency f

REF

Crystal or reference clock input. 25 MHz

Rise Time t

20% to 80%, C

= 10pF, 12.5MHz

(25MHz divided by 2), (Note 4)

2 ns

Fall Time t

80% to 20%, CL = 10pF, 12.5MHz

(25MHz divided by 2), (Note 4)

2 ns

Jitter t

= 10pF, Rising or falling edge,

12.5MHz (25MHz divided by 2)

100 ps (p-p)

AC ELECTRICAL CHARACTERISTICS / DIGITAL PLL OUTPUT (DPLL_OUT)

Frequency f

DPLL

Maximum 75

MHz

Minimum 1

Rise Time t

20% to 80%, C

= 10pF (Note 4) 2 ns

Fall Time t

80% to 20%, C

= 10pF (Note 4) 2 ns

Jitter t

Rising or falling edge, deterministic jitter +

14 x random jitter, 27MHz. (Note 4)

360 ps (p-p)

Note 1: Limits are 100% tested at T

= +105°C. Limits over the operating temperature range and relevant supply voltage range are

guaranteed by design and characterization.

Note 2: Not production tested. Guaranteed by design and characterization.

Note 3: Color bar pattern. Maximum supply currents are measured at indicated supply voltages. Typical supply currents are measured

at the typical supply voltages.

MAX96717 CSI-2 to GMSL2 Serializer

www.analog.com Analog Devices | 19

剩余234页未读，继续阅读

乐分享-程序员

粉丝: 784
资源: 22

MAX96717: GMSL视频串行器与双向控制通道的高速解决方案

max96717f_datasheet

单片K型热电偶放大与数字转换器MAX6675.pdf

max9286.pdf

3dmax白金手册.pdf

Spire.Pdf 纯图pdf

python aspose.pdf

matlab白化权函数,《灰色系统、白化规律和白化权函数.pdf》-支持高清全文免费浏览-max文档...

Kalman1960.pdf

COMPUTER ORGANIZATION AND DESIGN.pdf

最新资源