软核cortexM1/M3的FPGA实现介绍_cortex-m3移植soc

cortexM3

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Arm

Cortex

-M3 DesignStart

™

FPGA-

Xilinx edition

Revision: r0p0

User Guide

101483_0000_00_en

Arm

Cortex

-M3 DesignStart

™

FPGA-Xilinx edition

User Guide

Release Information

Document History

Issue Date Confidentiality Change

0000-00 29 October 2018 Non-Confidential First release for r0p0.

Non-Confidential Proprietary Notice

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110 Fulbourn Road, Cambridge, England CB1 9NJ.

LES-PRE-20349

Arm

Cortex

-M3 DesignStart

™

FPGA-Xilinx edition

Non-Confidential

Contents

Arm

Cortex

-M3 DesignStart

™

FPGA-Xilinx edition

User Guide

Preface

About this book ...................................................... ...................................................... 7

Feedback ...................................................................................................................... 9

Chapter 1 Introduction

1.1 Cortex

-M3 DesignStart

™

FPGA-Xilinx edition package .......................................... 1-11

1.2 Directory structure ................................................. ................................................. 1-12

1.3 Cortex

-M3 processor integration ............................................................................ 1-13

Chapter 2 Installing the Cortex

-M3 DesignStart

™

example design

2.1 Installing board files ................................................ ................................................ 2-15

2.2 Setting local drive for Windows ....................................... ....................................... 2-17

2.3 Installing Arm IP repository ...................................................................................... 2-18

2.4 Installing Arm software repository ..................................... ..................................... 2-19

2.5 Downloading QSPI memory models ........................................................................ 2-21

2.6 Configuring simulation in Vivado ...................................... ...................................... 2-23

Chapter 3 Cortex

-M3 processor IP configuration

3.1 Configuration tab .................................................. .................................................. 3-25

3.2 Debug tab ................................................................................................................ 3-27

3.3 Instruction Memory tab ............................................................................................ 3-29

3.4 Data Memory tab .................................................. .................................................. 3-31

Non-Confidential

3.5 Cortex

-M3 processor signals ........................................ ........................................ 3-33

Chapter 4 Working with the Cortex

-M3 DesignStart

™

example design

4.1 Editing the A7 example design ................................................................................ 4-36

4.2 Debug ...................................................................................................................... 4-37

4.3 Memory map ............................................................................................................ 4-38

4.4 QSPI multiplexing for the V2C-DAPLink board ........................... ........................... 4-41

4.5 Interrupt mapping .................................................................................................... 4-42

4.6 Constraints .............................................................................................................. 4-43

4.7 Loading the pre-built bitstream ................................................................................ 4-44

4.8 Loading the flash file ................................................................................................ 4-45

4.9 Bit file regeneration .................................................................................................. 4-47

4.10 Simulation ................................................................................................................ 4-48

Chapter 5 V2C-DAPLink board

5.1 V2C-DAPLink adaptor board features .................................. .................................. 5-50

5.2 V2C-DAPLink configuration .......................................... .......................................... 5-52

5.3 Flash download requirements ........................................ ........................................ 5-53

5.4 V2C-DAPLink board layout ...................................................................................... 5-54

5.5 Conditions to enable the DAP interface ................................. ................................. 5-56

5.6 DAP drivers ...................................................... ...................................................... 5-57

5.7 Programming the V2C-DAPLink QSPI using drag and drop ................. ................. 5-58

5.8 Using the μVision debugger to communicate through V2C-DAPLink .......... .......... 5-60

5.9 Using the μVision debugger to download projects through the flash programming

utility ........................................................................................................................ 5-62

5.10 Recovering the DAP connection .............................................................................. 5-65

Chapter 6 Example software design

6.1 Example software design for Arty A7 ................................... ................................... 6-68

6.2 Example software design directory structure ............................. ............................. 6-69

6.3 Example design reference files ....................................... ....................................... 6-70

6.4 Generating the Arty A7 board support package ...................................................... 6-71

6.5 Building the example software design .................................. .................................. 6-77

6.6 Software update flow ............................................... ............................................... 6-78

Appendix A Revisions

A.1 Revisions ................................................... ................................................... Appx-A-81

Non-Confidential

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