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Contents
1 Getting Started
Using a Verilog-A Device in a Simulation ................................................................. 1-1
Modifying a Verilog-A Device.................................................................................... 1-5
Overriding Model Parameters on Instances ....................................................... 1-7
Installing Verilog-A Based Devices Provided in a Design Kit.................................... 1-8
Licensing .................................................................................................................. 1-12
2 Using Verilog-A with the ADS Analog RF Simulator (ADSsim)
Loading Verilog-A modules....................................................................................... 2-1
The Auto Loading Mechanism............................................................................ 2-1
Explicit Loading of Verilog-A modules ................................................................ 2-2
Overriding Built-in Devices ....................................................................................... 2-3
Using Models with Verilog-A Devices ....................................................................... 2-4
The Verilog-A Compiled Model Library Cache ......................................................... 2-5
Controlling the Auto Compilation Process ................................................................ 2-7
Verilog-A Operator Limitations in Harmonic Balance and Circuit Envelope ............. 2-7
Module and Parameter Naming................................................................................ 2-8
Parameters ............................................................................................................... 2-8
Hierarchy and Module Resolution............................................................................. 2-9
Modifying the Simulator’s Model Search Path .......................................................... 2-9
The Compiler Include Search Path........................................................................... 2-9
Interaction with the Loading of Dynamically Linked UCMs....................................... 2-10
3 Introduction to Model Development in Verilog-A
Creating a Linear Resistor in Verilog-A .................................................................... 3-1
Adding Noise to the Verilog-A Resistor .............................................................. 3-2
Creating a Linear Capacitor and Inductor in Verilog-A ............................................. 3-3
Creating a Nonlinear Diode in Verilog-A................................................................... 3-4
Adding an Internal Node to the Diode ................................................................ 3-5
Adding Noise to the Diode.................................................................................. 3-6
Adding Limiting to the Diode for Better Convergence......................................... 3-6
Using Parameter Ranges to Restrict Verilog-A Parameter Values ........................... 3-7
Creating Sources in Verilog-A .................................................................................. 3-7
Creating Behavioral Models in Verilog-A .................................................................. 3-8
Using Hierarchy to Manage Model Complexity......................................................... 3-11
4 Migrating from the SDD and UCM
Symbolically Defined Devices .................................................................................. 4-1
User-Compiled Models............................................................................................. 4-8
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