IEEEStandard1364-1995HardwareDescriptionLanguage-Verilog

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Recognized as an

American National Standard (ANSI)

The Institute of Electrical and Electronics Engineers, Inc.

345 East 47th Street, New York, NY 10017-2394, USA

ISBN 1-55937-727-5

No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the prior

written permission of the publisher.

IEEE Std 1364-1995

IEEE Standard Hardware Description

Language Based on the Verilog

Hardware Description Language

Sponsor

Design Automation Standards Committee

of the

IEEE Computer Society

Approved 12 December 1995

IEEE Standards Board

Approved 1 August 1996

American National Standards Institute

Abstract:

The Verilog

Hardware Description Language (HDL) is defined. Verilog HDL is a formal

notation intended for use in all phases of the creation of electronic systems. Because it is both ma-

chine readable and human readable, it supports the development, verification, synthesis, and test-

ing of hardware designs; the communication of hardware design data; and the maintenance,

modification, and procurement of hardware. The primary audiences for this standard are the imple-

mentors of tools supporting the language and advanced users of the language.

Keywords:

computer, computer languages, electronic systems, digital systems, hardware, hard-

ware design, hardware description languages, HDL, programming language interface, PLI, Verilog

HDL, Verilog PLI, Verilog

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iii

Introduction

(This introduction is not a part of IEEE Std 1364-1995, IEEE Standard Hardware Description Language Based on the

Verilog

Hardware Description Language.)

The Verilog

Hardware Description Language (Verilog HDL) was designed to be simple, intuitive, and

effective at multiple levels of abstraction in a standard textual format for a variety of design tools, including

veriÞcation simulation, timing analysis, test analysis, and synthesis. The Verilog HDL was designed by Phil

Moorby during the winter of 1983Ð1984, and it was introduced into the EDA market in 1985 as the corner-

stone of a veriÞcation simulator product.

The Verilog HDL contains a rich set of built-in primitives, including logic gates, user-deÞnable primitives,

switches, and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract lev-

els is essentially provided by the semantics of two data types: nets and registers. Continuous assignments, in

which expressions of both registers and nets can continuously drive values onto nets, provide the basic struc-

tural construct. Procedural assignments, in which the results of calculations involving register and net values

can be stored into registers, provide the basic behavioral construct. A design consists of a set of modules,

each of which has an I/O interface and a description of its function, which can be structural, behavioral, or a

mix. These modules are formed into a hierarchy and are interconnected with nets.

The Verilog language is extensible via the Programming Language Interface (PLI). The PLI is a collection of

routines that allows foreign functions to access information contained in a Verilog HDL description of the

design and facilitates dynamic interaction with simulation. Applications of PLI include connecting to a Ver-

ilog HDL simulator with other simulation and CAD systems, customized debugging tasks, delay calculators,

and annotators.

The language that inßuenced Verilog HDL the most was HILO-2, which was developed at Brunel University

in England under a contract to produce a test generation system for the British Ministry of Defense. HILO-2

successfully combined the gate and register transfer levels of abstraction and supported veriÞcation simula-

tion, timing analysis, fault simulation, and test generation.

In 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independent Open

Verilog International (OVI) was formed to manage and promote Verilog HDL.

In 1992, the Board of Directors of OVI began an effort to establish Verilog HDL as an IEEE standard. With

many designers all over the world designing electronic circuits with Verilog HDL, this idea was enthusiasti-

cally received by the Verilog user community. When the Project Authorization Request (1364) was approved

by the IEEE in 1993, a working group was formed and the Þrst meeting was held on October 14, 1993.

Objective

The starting point for the IEEE P1364 Working Group were the OVI LRM version 2.0 and OVI PLI versions

1.0 and 2.0. The standardization process started with the clear objective of making it easier for the user to

understand and use Verilog. The IEEE P1364 standard had to be clear, unambiguous, implementable, and not

overly constraining. Since Verilog HDL has been in use for some time, it was quite robust enough to be pre-

sented to the user community without a great deal of enhancements. The working group, therefore, decided

not to spend a lot of time extending the language, but, for the purpose of this standardization, to concentrate

on clarifying the language.

Since Verilog HDL has been in widespread use and a number of ASIC vendors have built extensive libraries

in Verilog HDL, it was very important to maintain the integrity of these existing models. With this in mind, it

was decided that the intent of the working group would be to maintain the integrity of the standard and every

care would be taken not to invalidate existing models.

The standardization process

In order to clarify the language, many changes were proposed from a number of sources. The working group

met 15 times over a period of 18 months and voted on nearly 400 motions. Four drafts of the document were

generated and reviewed. It is a tribute to the hard work and dedication put forward by all the members of the

working group that this standard was completed in the short span of 18 months.

Many new sections were created, one of which is the section on scheduling semantics. A number of sections

were merged to form new sections. The two annexes containing compiler directives and system tasks were

moved into main text as two sections. Every effort has been made to clarify all ambiguities, add explana-

tions, and delete references that were deemed unnecessary.

Changes also included removing product speciÞc references and restrictions. The minimum product require-

ments for implementing this standard were clariÞed. A number of examples, Þgures, and tables were

retained in order to provide better context and explanation.

The PLI Task Force provided a clear and accurate description of OVI PLI 1.0 implementations already in

existence, and revisited the OVI PLI 2.0 speciÞcation to ensure its accuracy and completeness. The baseline

for the access routines and the task/function routines was the OVI PLI 1.0 speciÞcation. As there are a large

number of OVI PLI 1.0 routines in widespread use that were not included in the OVI PLI 1.0 document, it

was decided to consider additions to this document from the pool of existing OVI PLI 1.0 implementations.

The access routines and the task/function routines provide full backwards compatibility with Verilog HDL

software tools and PLI applications.

The baseline for the VPI routines was the existing OVI PLI 2.0 document. To this, the task force brought

new experience from the implementations in progress, which helped prove the worthiness of the previously

untested speciÞcation.

Acknowledgments

This standard is based on work originally developed by Cadence Design Systems, Inc. (in their Verilog LRM

1.6 and 2.0 and PLI documents) and Open Verilog International (in their Verilog LRM 2.0 and PLI 1.0 and

2.0). The IEEE is grateful to Cadence Design Systems and Open Verilog International for permission to use

their materials as the basis for this standard.

The IEEE Std 1364-1995 working group organization

Many individuals from many different organizations participated directly or indirectly in the standardization

process. The main body of the IEEE P1364 working group is located in the United States, with a subgroup in

Japan. Over a period of 18 months many task forces were created, of which the PLI task force was

prominent.

The members of the IEEE P1364 working group had voting privileges, and all motions had to be approved

by this group to be implemented. All task forces and subgroups focused on some speciÞc areas, and their

recommendations were eventually voted on by the IEEE P1364 working group.

At the time this document was approved, the IEEE P1364 working group had the following membership:

Maqsoodul (Maq) Mannan,

Chair

Yoshiharu Furui,

Vice Chair (Japan)

Alec G. Stanculescu,

Vice Chair (USA)

Lynn A. Horobin,

Secretary

Yatin Trivedi,

Technical Editor

Victor Berman John Mancini John Sanguinetti

Leigh Brady Michael McNamara Joseph P. Skudlarek

Clifford E. Cummings Elliot Mednick Stuart Sutherland

Peter Eichenberger Phil Moorby John R. Williamson

Andrew T. Lynch Gabe Moretti Alex N. ZamÞrescu

The PLI task force consisted of the following members:

Andrew T. Lynch,

PLI Task Force Leader

Stuart Sutherland,

Technical Editor

Charles A. Dawson Joel Paston Marco Zelado

Rajeev Madhavan Sathyam K. Pattanam Guoqing Zhang

David Roberts

The IEEE P1364 Japan subgroup consisted of the following members:

Yoshiharu Furui,

Vice-Chair, IEEE-1364 Working Group

Takaaki Akashi Junichi Murayama Toshiyuki Sakamoto

Kasumi Hamaguchi Masaharu Nakamura Hitomi Sato

Masato Ikeda Shouhei Oda Katsushida Seo

Masaru Kakimoto Fujio Otsuka Mitsuhiro Yasuda

Kazuya Morii Kazuhiro Yoshinaga

The following persons were members of the balloting group:

Guy Adam

H. Gordon Adshead

Unmesh Agarwala

Anant Agrawal

John Ainscough

Takaaki Akashi

Tom Albers

Glen Anderson

Lawrence F. Arnstein

Michael Atkin

Venkata Atluri

Rick Bahr

Jim Ball

Jose Baradiaran

Daniel S. Barclay

David L. Barton

Jean-Michel Berge

Victor Berman

J. Bhasker

Ron Bianchini

William D. Billowitch

Ronald D. Blanton

Miriam Blatt

James Brandt

Dennis B. Brophy

Randal E. Bryant

John A. Busco

Ben Buzonas

L. Richard Carley

Thomas Chao

Daniel Chapiro

Clive R. Charlwood

Chin-Fu Chen

Mojy C. Chian

Kai Moon Chow

Michael D. Ciletti

Joseph C. Circello

Luc Claesen

George M. Cleveland

Edmond S. Cooley

Tedd Corman

David Crohn

Clifford E. Cummings

Godfrey Paul D'Souza

Brian A. Dalio

Carlos Dangelo

Hal Daseking

Timothy R. Davis

Charles A. Dawson

Willem De Lange

Rajiv Deshmukh

Caroline DeVore-Kenney

Allen Dewey

Bill Doss

Douglas D. Dunlop

Peter Eichenberger

Hazem El Tahawy

John A. Eldon

Bassam N. Elkhoury

Ted Elkind

Brian Erickson

Robert A. Flatt

Bob Floyd

Alain Blaise Fonkoua

Douglas W. Forehand

Paul Franzon

Bill Fuchs

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2014-10-11

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