iii
Introduction
(This introduction is not a part of IEEE Std 1364-1995, IEEE Standard Hardware Description Language Based on the
Verilog
¨
Hardware Description Language.)
The Verilog
¨
Hardware Description Language (Verilog HDL) was designed to be simple, intuitive, and
effective at multiple levels of abstraction in a standard textual format for a variety of design tools, including
veriÞcation simulation, timing analysis, test analysis, and synthesis. The Verilog HDL was designed by Phil
Moorby during the winter of 1983Ð1984, and it was introduced into the EDA market in 1985 as the corner-
stone of a veriÞcation simulator product.
The Verilog HDL contains a rich set of built-in primitives, including logic gates, user-deÞnable primitives,
switches, and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract lev-
els is essentially provided by the semantics of two data types: nets and registers. Continuous assignments, in
which expressions of both registers and nets can continuously drive values onto nets, provide the basic struc-
tural construct. Procedural assignments, in which the results of calculations involving register and net values
can be stored into registers, provide the basic behavioral construct. A design consists of a set of modules,
each of which has an I/O interface and a description of its function, which can be structural, behavioral, or a
mix. These modules are formed into a hierarchy and are interconnected with nets.
The Verilog language is extensible via the Programming Language Interface (PLI). The PLI is a collection of
routines that allows foreign functions to access information contained in a Verilog HDL description of the
design and facilitates dynamic interaction with simulation. Applications of PLI include connecting to a Ver-
ilog HDL simulator with other simulation and CAD systems, customized debugging tasks, delay calculators,
and annotators.
The language that inßuenced Verilog HDL the most was HILO-2, which was developed at Brunel University
in England under a contract to produce a test generation system for the British Ministry of Defense. HILO-2
successfully combined the gate and register transfer levels of abstraction and supported veriÞcation simula-
tion, timing analysis, fault simulation, and test generation.
In 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independent Open
Verilog International (OVI) was formed to manage and promote Verilog HDL.
In 1992, the Board of Directors of OVI began an effort to establish Verilog HDL as an IEEE standard. With
many designers all over the world designing electronic circuits with Verilog HDL, this idea was enthusiasti-
cally received by the Verilog user community. When the Project Authorization Request (1364) was approved
by the IEEE in 1993, a working group was formed and the Þrst meeting was held on October 14, 1993.
Objective
The starting point for the IEEE P1364 Working Group were the OVI LRM version 2.0 and OVI PLI versions
1.0 and 2.0. The standardization process started with the clear objective of making it easier for the user to
understand and use Verilog. The IEEE P1364 standard had to be clear, unambiguous, implementable, and not
overly constraining. Since Verilog HDL has been in use for some time, it was quite robust enough to be pre-
sented to the user community without a great deal of enhancements. The working group, therefore, decided
not to spend a lot of time extending the language, but, for the purpose of this standardization, to concentrate
on clarifying the language.
Since Verilog HDL has been in widespread use and a number of ASIC vendors have built extensive libraries
in Verilog HDL, it was very important to maintain the integrity of these existing models. With this in mind, it
Authorized licensed use limited to: BEIJING INSTITUTE OF TECHNOLOGY. Downloaded on March 27,2020 at 11:07:04 UTC from IEEE Xplore. Restrictions apply.
评论0