μC/OS-II和dspic33

μC/OS-II

dspic33

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Micriµm

µC/OS-II

and the

Microchip dsPIC33

Application Note

AN-1033

www.Micrium.com

µC/OS-II and the Microchip dsPIC33

Table of Contents

1.00 Introduction ............................................................................................................. 3

2.00 The Microchip dsPIC33 programmer’s model ......................................................... 4

3.00 µC/OS-II Port for dsPIC33..................................................................................... 7

3.01 Directories and Files................................................................................................ 7

3.02 OS_CPU.H.............................................................................................................. 8

3.02.01 OS_CPU.H, macros for ‘externals’..................................................................... 8

3.02.02 OS_CPU.H, Data Types..................................................................................... 8

3.02.03 OS_CPU.H, Critical Sections ............................................................................. 9

3.02.04 OS_CPU.H, Stack growth .................................................................................. 9

3.02.05 OS_CPU.H, Task Level Context Switch............................................................. 9

3.02.06 OS_CPU.H, Function Prototypes ..................................................................... 10

3.03 OS_CPU_C.C ....................................................................................................... 10

3.03.01 OS_CPU_C.C, OSInitHookBegin()................................................................... 10

3.03.02 OS_CPU_C.C, OSInitHookEnd() ..................................................................... 11

3.03.03 OS_CPU_C.C, OSTaskCreateHook() .............................................................. 11

3.03.04 OS_CPU_C.C, OSTaskStkInit() ....................................................................... 12

3.03.05 OS_CPU_C.C, OSTaskSwHook().................................................................... 15

3.03.06 OS_CPU_C.C, OSTimeTickHook().................................................................. 15

3.04 OS_CPU_A.S........................................................................................................ 16

3.04.01 OS_CPU_A.S, OSStartHighRdy().................................................................... 16

3.04.02 OS_CPU_A.S, OSCtxSw()............................................................................... 17

3.04.03 OS_CPU_A.S, OSIntCtxSw()........................................................................... 18

3.04.04 OS_CPU_A.S, T2Interrupt()............................................................................. 18

3.04.05 OS_CPU_A.S, T4Interrupt()............................................................................. 19

3.05 OS_CPU_UTIL_A.S.............................................................................................. 20

3.06 OS_DBG.C............................................................................................................ 21

4.00 Interrupt Handling.................................................................................................. 22

5.00 Application Code ................................................................................................... 26

5.01 APP.C, APP.H and APP_CFG.H........................................................................... 27

5.02 INCLUDES.H......................................................................................................... 29

5.03 OS_CFG.H............................................................................................................ 29

6.00 BSP (Board Support Package).............................................................................. 30

7.00 Conclusion............................................................................................................. 31

Licensing ...................................................................................................................... 32

References.................................................................................................................... 32

Contacts ...................................................................................................................... 32

µC/OS-II and the Microchip dsPIC33

2.00 The Microchip dsPIC33 programmer’s model

This section provides a brief description of the dsPIC33 programmer’s model. We present enough

information in this section to provide a brief introduction. A complete description can be found in the

Microchip documentation.

The dsPIC33 family of CPU cores features proprietary Microchip architecture and is designed for

controller applications using a 16-bit (data), DSP capable architecture. Below are some of the features of

the dsPIC33 family of CPU cores:

• 16 General-purpose ‘Working’ registers

• Dual 40 bit Accumulators, 17x17 Multiplier

• 24 bit variable length instruction word, 23 bit program counter.

• 40 bit barrel shifter capable of 16 bit shift left of shift right in 1 cycle.

• Dedicated 1KB of DMA Ram

• Hardware divider support

• Dual Address generators for accessing memory blocks X and Y.

• High speed deterministic interrupt processing

The dsPIC33 is a Little Endian architecture and thus the least significant byte of a value is placed at a

lower memory location than its most significant byte.

Figure 2-1 shows the register model of the dsPIC33 and consist of 16 Working registers, two 40 bit

accumulators, the Data Table Page register, the Program Space Visibility Page Address register, a

Repeat Loop Counter, three dedicated DO Loop registers, the Core Configuration register, and a CPU

Status register.

W0-W15 (Working Registers)

• Registers W0-W3 are general purpose scratch pad registers

• Registers W4-W7 are the DSP Operand registers

• Registers W8-W11 are the DSP address registers

• Register W12 doubles as the DSP Offset register

• Register W13 doubles as the DSP Write Back register

• Register W14 doubles as the Frame Pointer register

• Register W15 doubles as the CPU Stack Pointer register

The stack pointer always points to the last pushed element. In other words, when an element is

pushed onto the stack, the stack pointer is first decremented and the value placed at the current

location where the stack is pointing to. The stack is popped by first reading the contents of the

stack and then incrementing the stack pointer.

SPLIM (Stack Pointer Limit Register)

• Causes a TRAP error when W15 is greater than SPLIM

ACCA / ACCB (DSP Accumulators)

• Dual 40 bit accumulators for DSP operations

TBLPAGE (Table Page Register)

• The 8-bit Table Page register (TBLPAG) is used to define a 32K word region within the program

space. This is concatenated with a 16-bit effective address in order to arrive at a full 24-bit

program space address.

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