没有合适的资源?快使用搜索试试~ 我知道了~
首页PCIe spec 1.0a
PCIe spec 1.0a
4星 · 超过85%的资源 需积分: 9 96 下载量 4 浏览量
更新于2023-03-03
评论
收藏 3.29MB PDF 举报
PCI3 spec. 1.0a PCI3 spec. 1.0a PCI3 spec. 1.0a
资源详情
资源评论
资源推荐
PCI Express
™
Base Specification
Revision 1.0a
April 15, 2003
2
Revision Revision History DATE
1.0 Initial release. 7/22/02
1.0a Incorporated Errata C1-C67 and E1-E4.17. 04/15/03
PCI-SIG disclaims all warranties and liability for the use of this document and the information
contained herein and assumes no responsibility for any errors that may appear in this document, nor
does PCI-SIG make a commitment to update the information contained herein.
Contact the PCI-SIG office to obtain the latest revision of this specification.
Questions regarding the PCI Express Base Specification or membership in PCI-SIG may be
forwarded to:
Membership Services
www.pcisig.com
E-mail: administration@pcisig.com
Phone: 1-800-433-5177 (Domestic Only)
+503-291-2569
Fax: 503-297-1090
Technical Support
techsupp@pcisig.com
DISCLAIMER
This PCI Express Base Specification is provided "as is" with no warranties whatsoever,
including any warranty of merchantability, noninfringement, fitness for any particular
purpose, or any warranty otherwise arising out of any proposal, specification, or sample.
PCI-SIG disclaims all liability for infringement of proprietary rights, relating to use of
information in this specification. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted herein.
PCI Express is a trademark of PCI-SIG.
All other product names are trademarks, registered trademarks, or servicemarks of their respective
owners.
Copyright © 2002, 2003 PCI-SIG
PCI EXPRESS BASE SPECIFICATION, REV 1.0a
3
Contents
OBJECTIVE OF THE SPECIFICATION .................................................................................... 17
DOCUMENT ORGANIZATION................................................................................................. 17
DOCUMENTATION CONVENTIONS ...................................................................................... 18
TERMS AND ACRONYMS ........................................................................................................ 19
REFERENCE DOCUMENTS ...................................................................................................... 25
1. INTRODUCTION................................................................................................................. 27
1.1. A T
HIRD
G
ENERATION
I/O I
NTERCONNECT
................................................................... 27
1.2. PCI E
XPRESS
L
INK
......................................................................................................... 29
1.3. PCI E
XPRESS
F
ABRIC
T
OPOLOGY
.................................................................................. 30
1.3.1. Root Complex ........................................................................................................ 31
1.3.2. Endpoints............................................................................................................... 32
1.3.3. Switch .................................................................................................................... 33
1.3.4. PCI Express-PCI Bridge ....................................................................................... 34
1.4. PCI E
XPRESS
F
ABRIC
T
OPOLOGY
C
ONFIGURATION
....................................................... 34
1.5. PCI E
XPRESS
L
AYERING
O
VERVIEW
.............................................................................. 34
1.5.1. Transaction Layer ................................................................................................. 36
1.5.2. Data Link Layer .................................................................................................... 36
1.5.3. Physical Layer....................................................................................................... 36
1.5.4. Layer Functions and Services ............................................................................... 37
2. TRANSACTION LAYER SPECIFICATION...................................................................... 41
2.1. T
RANSACTION
L
AYER
O
VERVIEW
.................................................................................. 41
2.1.1. Address Spaces, Transaction Types, and Usage...................................................42
2.1.2. Packet Format Overview....................................................................................... 44
2.2. T
RANSACTION
L
AYER
P
ROTOCOL
- P
ACKET
D
EFINITION
............................................... 45
2.2.1. Common Packet Header Fields............................................................................. 45
2.2.2. TLPs with Data Payloads - Rules ......................................................................... 48
2.2.3. TLP Digest Rules................................................................................................... 49
2.2.4. Routing and Addressing Rules .............................................................................. 49
2.2.5. First/Last DW Byte Enables Rules ........................................................................ 52
2.2.6. Transaction Descriptor ......................................................................................... 54
2.2.7. Memory, I/O, and Configuration Request Rules ................................................... 59
2.2.8. Message Request Rules ......................................................................................... 62
2.2.9. Completion Rules .................................................................................................. 74
PCI EXPRESS BASE SPECIFICATION, REV 1.0a
4
2.3. H
ANDLING OF
R
ECEIVED
TLP
S
...................................................................................... 76
2.3.1. Request Handling Rules ........................................................................................ 79
2.3.2. Completion Handling Rules .................................................................................. 89
2.4. T
RANSACTION
O
RDERING
.............................................................................................. 90
2.4.1. Transaction Ordering Rules.................................................................................. 90
2.4.2. Update Ordering and Granularity Observed by a Read Transaction .................. 93
2.4.3. Update Ordering and Granularity Provided by a Write Transaction .................. 94
2.5. V
IRTUAL
C
HANNEL
(VC) M
ECHANISM
.......................................................................... 95
2.5.1. Virtual Channel Identification (VC ID) ................................................................ 97
2.5.2. TC to VC Mapping ................................................................................................ 98
2.5.3. VC and TC Rules................................................................................................... 99
2.6. O
RDERING AND
R
ECEIVE
B
UFFER
F
LOW
C
ONTROL
...................................................... 100
2.6.1. Flow Control Rules ............................................................................................. 101
2.7. D
ATA
I
NTEGRITY
......................................................................................................... 110
2.7.1. ECRC Rules......................................................................................................... 110
2.7.2. Error Forwarding ............................................................................................... 114
2.8. C
OMPLETION
T
IMEOUT
M
ECHANISM
........................................................................... 116
2.9. L
INK
S
TATUS
D
EPENDENCIES
....................................................................................... 117
2.9.1. Transaction Layer Behavior in DL_Down Status............................................... 117
2.9.2. Transaction Layer Behavior in DL_Up Status .................................................... 118
3. DATA LINK LAYER SPECIFICATION .......................................................................... 119
3.1. D
ATA
L
INK
L
AYER
O
VERVIEW
.................................................................................... 119
3.2. D
ATA
L
INK
C
ONTROL AND
M
ANAGEMENT
S
TATE
M
ACHINE
....................................... 121
3.2.1. Data Link Control and Management State Machine Rules................................. 122
3.3. F
LOW
C
ONTROL
I
NITIALIZATION
P
ROTOCOL
................................................................ 123
3.3.1. Flow Control Initialization State Machine Rules................................................ 125
3.4. D
ATA
L
INK
L
AYER
P
ACKETS
(DLLP
S
) ........................................................................ 128
3.4.1. Data Link Layer Packet Rules............................................................................. 128
3.5. D
ATA
I
NTEGRITY
......................................................................................................... 132
3.5.1. Introduction......................................................................................................... 132
3.5.2. LCRC, Sequence Number, and Retry Management (TLP Transmitter).............. 133
3.5.3. LCRC and Sequence Number (TLP Receiver) .................................................... 145
4. PHYSICAL LAYER SPECIFICATION ............................................................................ 151
4.1. I
NTRODUCTION
............................................................................................................. 151
4.2. L
OGICAL
S
UB
-
BLOCK
................................................................................................... 151
4.2.1. Symbol Encoding................................................................................................. 152
4.2.2. Framing and Application of Symbols to Lanes ................................................... 155
4.2.3. Data Scrambling ................................................................................................. 158
4.2.4. Link Initialization and Training .......................................................................... 159
4.2.5. Link Training and Status State Machine (LTSSM) Descriptions ........................ 167
4.2.6. Link Training and Status State Rules .................................................................. 170
4.2.7. Clock Tolerance Compensation .......................................................................... 200
4.2.8. Compliance Pattern............................................................................................. 201
PCI EXPRESS BASE SPECIFICATION, REV 1.0a
5
4.3. E
LECTRICAL
S
UB
-
BLOCK
............................................................................................. 202
4.3.1. Electrical Sub-Block Requirements.....................................................................202
4.3.2. Electrical Signal Specifications .......................................................................... 206
4.3.3. Differential Transmitter (TX) Output Specifications .......................................... 211
4.3.4. Differential Receiver (RX) Input Specifications.................................................. 216
5. POWER MANAGEMENT ................................................................................................. 221
5.1. O
VERVIEW
................................................................................................................... 221
5.1.1. Statement of Requirements .................................................................................. 222
5.2. L
INK
S
TATE
P
OWER
M
ANAGEMENT
............................................................................. 222
5.3. PCI-PM S
OFTWARE
C
OMPATIBLE
M
ECHANISMS
......................................................... 227
5.3.1. Device Power Management States (D-States) of a Function.............................. 227
5.3.2. PM Software Control of the Link Power Management State.............................. 230
5.3.3. Power Management Event Mechanisms ............................................................. 235
5.4. N
ATIVE
PCI E
XPRESS
P
OWER
M
ANAGEMENT
M
ECHANISMS
....................................... 242
5.4.1. ASPM................................................................................................................... 243
5.5. A
UXILIARY
P
OWER
S
UPPORT
....................................................................................... 257
5.5.1. Auxiliary Power Enabling................................................................................... 257
5.6. P
OWER
M
ANAGEMENT
S
YSTEM
M
ESSAGES AND
DLLP
S
............................................. 258
6. SYSTEM ARCHITECTURE.............................................................................................. 259
6.1. I
NTERRUPT AND
PME S
UPPORT
................................................................................... 259
6.1.1. Rationale for PCI Express Interrupt Model........................................................ 259
6.1.2. PCI Compatible INTx Emulation ........................................................................ 260
6.1.3. INTx Emulation Software Model......................................................................... 260
6.1.4. Message Signaled Interrupt (MSI) Support ........................................................260
6.1.5. PME Support ....................................................................................................... 261
6.1.6. Native PME Software Model............................................................................... 261
6.1.7. Legacy PME Software Model.............................................................................. 261
6.1.8. Operating System Power Management Notification........................................... 262
6.1.9. PME Routing Between PCI Express and PCI Hierarchies................................. 262
6.2. E
RROR
S
IGNALING AND
L
OGGING
................................................................................ 263
6.2.1. Scope ................................................................................................................... 263
6.2.2. Error Classification ............................................................................................ 263
6.2.3. Error Signaling ................................................................................................... 265
6.2.4. Error Logging ..................................................................................................... 267
6.2.5. Sequence of Device Error Signaling and Logging Operations........................... 269
6.2.6. Error Listing and Rules....................................................................................... 270
6.2.7. Virtual PCI Bridge Error Handling.................................................................... 273
6.3. V
IRTUAL
C
HANNEL
S
UPPORT
....................................................................................... 273
6.3.1. Introduction and Scope ....................................................................................... 273
6.3.2. TC/VC Mapping and Example Usage ................................................................. 274
6.3.3. VC Arbitration..................................................................................................... 276
6.3.4. Isochronous Support ........................................................................................... 283
6.4. D
EVICE
S
YNCHRONIZATION
......................................................................................... 285
剩余425页未读,继续阅读
seacloud
- 粉丝: 4
- 资源: 5
上传资源 快速赚钱
- 我的内容管理 收起
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
会员权益专享
最新资源
- RTL8188FU-Linux-v5.7.4.2-36687.20200602.tar(20765).gz
- c++校园超市商品信息管理系统课程设计说明书(含源代码) (2).pdf
- 建筑供配电系统相关课件.pptx
- 企业管理规章制度及管理模式.doc
- vb打开摄像头.doc
- 云计算-可信计算中认证协议改进方案.pdf
- [详细完整版]单片机编程4.ppt
- c语言常用算法.pdf
- c++经典程序代码大全.pdf
- 单片机数字时钟资料.doc
- 11项目管理前沿1.0.pptx
- 基于ssm的“魅力”繁峙宣传网站的设计与实现论文.doc
- 智慧交通综合解决方案.pptx
- 建筑防潮设计-PowerPointPresentati.pptx
- SPC统计过程控制程序.pptx
- SPC统计方法基础知识.pptx
资源上传下载、课程学习等过程中有任何疑问或建议,欢迎提出宝贵意见哦~我们会及时处理!
点击此处反馈
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功
评论6