DDR4 SDRAM SODIMM Design Specification

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DDR4 SDRAM SODIMM Design Specification, DDR4笔记本内存条jedec标准设计规范

JEDEC Standard No. 21C

Page 4.20.25-1

Release 26 Revision 1.20

4.20.25 - 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/

PC4-2666/PC4-3200 DDR4 SDRAM SO-DIMM Design Specification

DDR4 SDRAM SO-DIMM Design Specification

Revision 1.20

June 2016

Revision 1.20 Release 26

JEDEC Standard No. 21C

Page 4.20.25-2

Table of Contents

1 Product Description .......................................................................................................... 5

2 Environmental Requirements........................................................................................... 6

3 Connector Pinout and Signal Description....................................................................... 7

3.1 DDR4 SO-DIMM Connector Pin Assignments .....................................................................................10

4 Power Details ................................................................................................................... 12

4.1 DIMM Voltage Requirements ................................................................................................................12

4.2 Rules for Power-Up Sequence..............................................................................................................13

4.3 Feed Through Voltage (VFT).................................................................................................................13

5 Component Details.......................................................................................................... 15

5.1 Component Types and Placement .......................................................................................................18

5.2 Decoupling Guidelines..........................................................................................................................18

6 DIMM Design Details ....................................................................................................... 19

6.1 Signal Groups ........................................................................................................................................19

6.2 Explanation of Net Structure Diagrams...............................................................................................19

6.3 General Net Structure Routing Rules ..................................................................................................20

6.3.1 Clock, Control, and Address/Command Groups ........................................................... 20

6.3.2 Lead-in vs. Loaded Sections ......................................................................................... 21

6.3.3 Length/Delay Matching to SDRAM Devices..................................................................21

6.3.4 Velocity Compensation.................................................................................................. 22

6.3.5 Load/Delay Compensation ............................................................................................22

6.3.6 Data and Strobe Group .................................................................................................22

6.3.7 ALERT_n Wiring............................................................................................................23

6.3.8 Via Compensation .........................................................................................................23

6.3.9 Plane Referencing.........................................................................................................25

6.4 Address Mirroring..................................................................................................................................25

6.5 DIMM Routing Space Constraints ........................................................................................................26

6.6 DIMM Physical Requirements...............................................................................................................27

6.6.1 Via Size .........................................................................................................................27

6.6.2 Component Pad Sizes and Geometry...........................................................................27

6.6.3 DRAM Package Size .....................................................................................................27

6.6.4 Clock Termination .........................................................................................................27

6.6.5 ZQ Calibration Wiring ....................................................................................................27

6.6.6 DQ Stub Resistor ..........................................................................................................28

6.6.7 TEN Wiring ....................................................................................................................28

6.7 Reference Stackups...............................................................................................................................28

6.8 Impedance Targets ................................................................................................................................30

6.9 SPD Wiring and Placement ...................................................................................................................31

6.10 DQ Mapping to Support CRC................................................................................................................32

7 Serial Presence Detect Component Specification........................................................ 35

7.1 Serial Presence Detect Definition.........................................................................................................35

8 Product Label................................................................................................................... 37

8.1 DDR4 DIMM Label Format for DRAM-only module types...................................................................37

8.2 DDR4 DIMM Label Format for Hybrid module types...........................................................................41

9 JEDEC Process................................................................................................................ 44

JEDEC Standard No. 21C

Page 4.20.25-3

Release 26 Revision 1.20

List of Tables

Table 1 — Product Family Attributes............................................................................................................ 5

Table 2 — Environmental Parameters .......................................................................................................... 6

Table 3 — Connector Pin Definition ............................................................................................................. 7

Table 4 — Input/Output Functional Description .......................................................................................... 8

Table 5 — DDR4 SO-DIMM 260 Pin Connector Pin Wiring Assignments................................................ 10

Table 6 — DDR4 SO-DIMM DC Operating Voltage1,2,3 - 1.2 V operation................................................ 12

Table 7 — DDR4 x8 SDRAM DIMM Pad Array ............................................................................................ 16

Table 8 — DDR4 x16 SDRAM DIMM Pad Array .......................................................................................... 17

Table 9 — DDR4 SO-DIMM Decoupling Capacitor Guidelines ................................................................. 18

Table 10 — CK, CTRL, and ADD/CMD Group Length Matching Rules .................................................... 20

Table 11 — Data and Strobe Group Length Matching Rules.................................................................... 22

Table 12 — Plane Referencing .................................................................................................................... 25

Table 13 — DIMM Wiring Definition for Address Mirroring ...................................................................... 25

Table 14 — Routing Space Constraints ..................................................................................................... 26

Table 15 — Preferred 10 Layer Stackup for SO-DIMMs ............................................................................ 28

Table 16 — Preferred 8 Layer Stackup for SO-DIMMs .............................................................................. 29

Table 17 — Preferred 6 Layer Stackup for SO-DIMMs .............................................................................. 29

Table 18 — Impedance Assignments by Signal Type............................................................................... 30

Table 19 — SPD DQ Nibble Map for CRC ................................................................................................... 32

Table 20 — Nibble/Byte DQ Map Patterns for CRC ................................................................................... 33

Table 21 — Example of DQ Mapping for CRC............................................................................................ 34

Table 22 — SPD Address Map..................................................................................................................... 35

Table 23 — Block 0: Base Configuration and DRAM Parameters............................................................ 35

Table 24 — Preproduction Registration Table........................................................................................... 39

JEDEC Standard No. 21C

Page 4.20.25-5

Release 26 Revision 1.20

1 Product Description

This specification defines the electrical and mechanical requirements for 260 pin, 1.2 V (VDD), Small Outline,

Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SO-DIMMs). These

DDR4 SO-DIMMs are intended for use as main memory when installed in PCs, laptops and other systems.

Reference design examples are included which provide an initial basis for DDR4 SO-DIMM designs.

Modifications to these reference designs may be required to meet all system timing, signal integrity and

thermal requirements for PC4-1600, PC4-1866, PC4-2133, PC4-2400, PC4-2666 and PC4-3200 support. All

DDR4 SO-DIMM implementations must use simulations and lab verification to ensure proper timing

requirements and signal integrity in the design.

This specification follows the JEDEC standard DDR4 component specification (refer to JEDEC standard

JESD79-4, at www.jedec.org).

Table 1 — Product Family Attributes

DIMM Organization x64, x72 ECC Notes

DIMM Dimensions

(nominal)

69.6 mm x 30.0 mm

Refer to MO-310

2 mm wider than DDR3

Pin Count and Pitch 260 on 0.5 mm centers

DDR4 SDRAMs Sup-

ported

4 Gb, 8 Gb, 12 Gb, 16 Gb, 24 Gb, 32 Gb,

64 Gb

78/106-ball FBGA package for x8 and 96/112-ball FBGA for

x16 devices.

Refer to MO-207:

x8 variations DT-z, DW-z

x16 variations DU-z, DY-z

Capacity 2 GB - 256 GB SDP - 32 GB max, 3DS -256 GB max

DDR4 SDRAM width x8, x16

Serial Presence Detect,

Thermal Sensor (SPD-

TSE/SPD)

512 byte See EE1004-v and TSE2004av specifications

Voltage Options

PC4 - 1.2 V for VDD

All DDR4 modules use a common VDD–VDDQ power plane.

They are tied together on the DIMM, but by standard definition

are supported on the pinout to accommodate future enhance-

ments.

PC4 - 0.6 V for VTT

Termination voltage for Address, Command, and Control.

2.5 V for VPP

This supply has VSS as its return path. On DIMM It is treated

as a separate supply from VDDSPD.

2.5 V or 3.3 V for VDDSPD SPD supply is operable with 2.5 V or 3.3 V.

Interface 1.2 V signaling

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