PCI BUS POWER MANAGEMENT INTERFACE SPECIFICATION, REV. 1.2
4
5. PCI FUNCTION POWER MANAGEMENT STATES ................................................ 41
5.1. PCI F
UNCTION
D0
S
TATE
............................................................................................. 41
5.2. PCI F
UNCTION
D1 S
TATE
............................................................................................ 41
5.3. PCI F
UNCTION
D2 S
TATE
............................................................................................ 42
5.4. PCI F
UNCTION
D3 S
TATE
............................................................................................ 42
5.4.1. Software Accessible D3 (D3
hot
)........................................................................... 43
5.4.2. Power Off (D3
cold
) ............................................................................................... 43
5.4.3. 3.3Vaux/D3
cold
Add-in Card Power Consumption Requirements ....................... 44
5.5. PCI F
UNCTION
P
OWER
S
TATE
T
RANSITIONS
................................................................ 45
5.6. PCI F
UNCTION
P
OWER
M
ANAGEMENT
P
OLICIES
.......................................................... 45
5.6.1. State Transition Recovery Time Requirements ................................................... 50
6. PCI BRIDGES AND POWER MANAGEMENT .......................................................... 53
6.1. H
OST
B
RIDGE OR
O
THER
S
YSTEM
B
OARD
E
NUMERATED
B
RIDGE
................................ 55
6.2. PCI-
TO
-PCI B
RIDGES
................................................................................................... 56
6.3. PCI-
TO
-C
ARD
B
US
B
RIDGE
........................................................................................... 56
7. POWER MANAGEMENT EVENTS.............................................................................. 57
7.1. P
OWER
M
ANAGEMENT
E
VENT
(PME#) S
IGNAL
R
OUTING
........................................... 60
7.2. A
UXILIARY
P
OWER
....................................................................................................... 61
7.2.1. 3.3Vaux DC Characteristics ............................................................................... 61
7.2.2. 3.3Vaux Minimum Required Current Capacity................................................... 62
7.3. 3.3V
AUX
S
YSTEM
D
ESIGN
R
EQUIREMENTS
.................................................................. 62
7.3.1. Power Delivery Requirements............................................................................. 62
7.3.2. PCI Bus RST# Signaling Requirements .............................................................. 63
7.3.3. Voltage Sequencing ............................................................................................. 64
7.4. 3.3V
AUX
A
DD
-
IN
C
ARD
D
ESIGN
R
EQUIREMENTS
......................................................... 65
7.4.1. 3.3Vaux Power Consumption Requirements....................................................... 65
7.4.2. Physical Connection to the 3.3Vaux Pin............................................................. 65
7.4.3. Isolation of 3.3Vaux from Main 3.3V.................................................................. 65
7.4.4. 3.3Vaux Presence Detection................................................................................ 66
8. SOFTWARE SUPPORT FOR PCI POWER MANAGEMENT .................................. 67
8.1. I
DENTIFYING
PCI F
UNCTION
C
APABILITIES
.................................................................. 67
8.2. P
LACING
PCI F
UNCTIONS IN A
L
OW
P
OWER
S
TATE
...................................................... 67
8.2.1. Buses.................................................................................................................... 68
8.2.2. D3 State............................................................................................................... 68
8.3. R
ESTORING
PCI F
UNCTIONS
F
ROM A
L
OW
P
OWER
S
TATE
............................................ 69
8.3.1. D0 “Uninitialized” and the DSI Bit.................................................................... 69
8.3.2. D1 and D2 States................................................................................................. 70
8.3.3. D3 State............................................................................................................... 70
8.4. W
AKE
E
VENTS
............................................................................................................. 70
8.4.1. Wake Event Support ............................................................................................ 70
8.4.2. The D0 “Initialized” State From a Wake Event.................................................. 71
8.5. G
ET
C
APABILITIES
........................................................................................................ 71