PCI PM Spec

Power

Mangement

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PCI Power Management Specification 1.2

PCI Bus Power Management

Interface Specification

Revision 1.2

March 3, 2004

PCI BUS POWER MANAGEMENT INTERFACE SPECIFICATION, REV. 1.2

Contents

1. INTRODUCTION............................................................................................................... 7

1.1. G

OALS OF

HIS

PECIFICATION

...................................................................................... 7

1.2. T

ARGET

UDIENCE

........................................................................................................ 8

1.3. O

VERVIEW

COPE

.......................................................................................................... 9

1.4. C

ONVENTIONS

SED IN

HIS

OCUMENT

..................................................................... 10

1.5. G

LOSSARY OF

ERMS

................................................................................................... 10

1.6. R

ELATED

OCUMENTS

................................................................................................. 15

2. PCI POWER MANAGEMENT OVERVIEW ............................................................... 17

2.1. PCI P

OWER

ANAGEMENT

TATES

............................................................................. 17

2.1.1. PCI Function Power States ................................................................................. 17

2.1.2. Bus Power States................................................................................................. 17

2.1.3. PCI Express Link Power States........................................................................... 17

2.1.4. Device-Class Specifications ................................................................................ 18

2.1.5. Bus Support for PCI Function Power Management ........................................... 19

3. PCI POWER MANAGEMENT INTERFACE .............................................................. 21

3.1. C

APABILITIES

IST

ATA

TRUCTURE

.......................................................................... 22

3.1.1. Capabilities List Cap_Ptr Location .................................................................... 23

3.2. P

OWER

ANAGEMENT

EGISTER

LOCK

EFINITION

.................................................. 24

3.2.1. Capability Identifier - Cap_ID (Offset = 0) ........................................................ 24

3.2.2. Next Item Pointer - Next_Item_Ptr (Offset = 1).................................................. 25

3.2.3. PMC - Power Management Capabilities (Offset = 2) ........................................ 25

3.2.4. PMCSR - Power Management Control/Status (Offset = 4) ................................ 27

3.2.5. PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions (Offset = 6).... 30

3.2.6. Data (Offset = 7)................................................................................................. 31

4. PCI BUS POWER STATES............................................................................................. 35

4.1. PCI B0 S

TATE

- F

ULLY

.......................................................................................... 36

4.2. PCI B1 S

TATE

.............................................................................................................. 36

4.3. PCI B2 S

TATE

.............................................................................................................. 36

4.4. PCI B3 S

TATE

- O

.................................................................................................... 37

4.5. PCI B

OWER

TATE

RANSITIONS

.......................................................................... 37

4.6. PCI C

LOCKING

ONSIDERATIONS

................................................................................ 38

4.6.1. Special Considerations for 66-MHz PCI Designs............................................... 38

4.7. C

ONTROL

TATUS OF

PCI B

OWER

ANAGEMENT

TATES

................................... 39

4.7.1. Control of Secondary Bus Power Source and Clock........................................... 39

PCI BUS POWER MANAGEMENT INTERFACE SPECIFICATION, REV. 1.2

5. PCI FUNCTION POWER MANAGEMENT STATES ................................................ 41

5.1. PCI F

UNCTION

TATE

............................................................................................. 41

5.2. PCI F

UNCTION

D1 S

TATE

............................................................................................ 41

5.3. PCI F

UNCTION

D2 S

TATE

............................................................................................ 42

5.4. PCI F

UNCTION

D3 S

TATE

............................................................................................ 42

5.4.1. Software Accessible D3 (D3

hot

)........................................................................... 43

5.4.2. Power Off (D3

cold

) ............................................................................................... 43

5.4.3. 3.3Vaux/D3

cold

Add-in Card Power Consumption Requirements ....................... 44

5.5. PCI F

UNCTION

OWER

TATE

RANSITIONS

................................................................ 45

5.6. PCI F

UNCTION

OWER

ANAGEMENT

OLICIES

.......................................................... 45

5.6.1. State Transition Recovery Time Requirements ................................................... 50

6. PCI BRIDGES AND POWER MANAGEMENT .......................................................... 53

6.1. H

OST

RIDGE OR

THER

YSTEM

OARD

NUMERATED

RIDGE

................................ 55

6.2. PCI-

-PCI B

RIDGES

................................................................................................... 56

6.3. PCI-

-C

ARD

RIDGE

........................................................................................... 56

7. POWER MANAGEMENT EVENTS.............................................................................. 57

7.1. P

OWER

ANAGEMENT

VENT

(PME#) S

IGNAL

OUTING

........................................... 60

7.2. A

UXILIARY

OWER

....................................................................................................... 61

7.2.1. 3.3Vaux DC Characteristics ............................................................................... 61

7.2.2. 3.3Vaux Minimum Required Current Capacity................................................... 62

7.3. 3.3V

AUX

YSTEM

ESIGN

EQUIREMENTS

.................................................................. 62

7.3.1. Power Delivery Requirements............................................................................. 62

7.3.2. PCI Bus RST# Signaling Requirements .............................................................. 63

7.3.3. Voltage Sequencing ............................................................................................. 64

7.4. 3.3V

AUX

ARD

ESIGN

EQUIREMENTS

......................................................... 65

7.4.1. 3.3Vaux Power Consumption Requirements....................................................... 65

7.4.2. Physical Connection to the 3.3Vaux Pin............................................................. 65

7.4.3. Isolation of 3.3Vaux from Main 3.3V.................................................................. 65

7.4.4. 3.3Vaux Presence Detection................................................................................ 66

8. SOFTWARE SUPPORT FOR PCI POWER MANAGEMENT .................................. 67

8.1. I

DENTIFYING

PCI F

UNCTION

APABILITIES

.................................................................. 67

8.2. P

LACING

PCI F

UNCTIONS IN A

OWER

TATE

...................................................... 67

8.2.1. Buses.................................................................................................................... 68

8.2.2. D3 State............................................................................................................... 68

8.3. R

ESTORING

PCI F

UNCTIONS

ROM A

OWER

TATE

............................................ 69

8.3.1. D0 “Uninitialized” and the DSI Bit.................................................................... 69

8.3.2. D1 and D2 States................................................................................................. 70

8.3.3. D3 State............................................................................................................... 70

8.4. W

AKE

VENTS

............................................................................................................. 70

8.4.1. Wake Event Support ............................................................................................ 70

8.4.2. The D0 “Initialized” State From a Wake Event.................................................. 71

8.5. G

APABILITIES

........................................................................................................ 71

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