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PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.7
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9.3.6 Data Rate Dependent Parameters ........................................................................ 1143
9.3.7 Tx and Rx Return Loss .......................................................................................... 1147
9.3.8 Transmitter PLL Bandwidth and Peaking ............................................................ 1148
9.3.9 Data Rate Independent Tx Parameters ................................................................. 1149
9.4 RECEIVER SPECIFICATIONS ........................................................................................ 1150
9.4.1 Receiver Stressed Eye Specification ..................................................................... 1150
9.4.2 Stressed Eye Test ................................................................................................... 1156
9.4.3 Common Receiver Parameters ............................................................................. 1164
9.4.4 Lane Margining at the Receiver ........................................................................... 1167
9.4.5 Low Frequency and Miscellaneous Signaling Requirements ............................... 1169
9.5 CHANNEL TOLERANCING ........................................................................................... 1172
9.5.1 Channel Compliance Testing ................................................................................ 1172
9.6 REFCLK SPECIFICATIONS ........................................................................................... 1182
9.6.1 Refclk Test Setup ................................................................................................... 1182
9.6.2 REFCLK AC Specifications .................................................................................. 1183
9.6.3 Data Rate Independent Refclk Parameters ........................................................... 1186
9.6.4 Refclk Architectures Supported ............................................................................. 1187
9.6.5 Filtering Functions Applied to Raw Data ............................................................. 1187
9.6.6 Common Refclk Rx Architecture (CC) .................................................................. 1189
9.6.7 Jitter Limits for Refclk Architectures .................................................................... 1192
10 SINGLE ROOT I/O VIRTUALIZATION AND SHARING ...................................... 1194
10.1 ARCHITECTURAL OVERVIEW ..................................................................................... 1194
10.1.1 PCI Technologies Interoperability ................................................................... 1206
10.2 INITIALIZATION AND RESOURCE ALLOCATION .......................................................... 1207
10.2.1 SR-IOV Resource Discovery ............................................................................. 1207
10.2.2 Reset Mechanisms ............................................................................................. 1212
10.2.3 IOV Re-initialization and Reallocation ............................................................ 1212
10.2.4 VF Migration .................................................................................................... 1212
10.3 CONFIGURATION ........................................................................................................ 1216
10.3.1 Overview ........................................................................................................... 1216
10.3.2 Configuration Space ......................................................................................... 1216
10.3.3 SR-IOV Extended Capability ............................................................................ 1216
10.3.4 PF/VF Configuration Space Header ................................................................ 1235
10.3.5 PCI Express Capability ..................................................................................... 1240
10.3.6 PCI Standard Capabilities ................................................................................ 1250
10.3.7 PCI Express Extended Capabilities .................................................................. 1251
10.4 ERROR HANDLING ..................................................................................................... 1259
10.4.1 Baseline Error Reporting .................................................................................. 1259
10.4.2 Advanced Error Reporting ................................................................................ 1260
10.5 INTERRUPTS ............................................................................................................... 1266
10.5.1 Interrupt Mechanisms ....................................................................................... 1266
10.6 POWER MANAGEMENT ............................................................................................... 1267
10.6.1 VF Device Power Management States .............................................................. 1267
10.6.2 PF Device Power Management States .............................................................. 1268
10.6.3 Link Power Management State ......................................................................... 1269
10.6.4 VF Power Management Capability .................................................................. 1269