没有合适的资源?快使用搜索试试~ 我知道了~
首页DDR3 SDRAM Standard(DDR3设计规范)
资源详情
资源评论
资源推荐
JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
JESD79-3A
September 2007
JEDEC
STANDARD
DDR3 SDRAM Specification
(Revision of JESD79-3)
NOTICE
JEDEC standards and publications contain material that has been prepared, reviewed, and
approved through the JEDEC Board of Directors level and subsequently reviewed and approved
by the JEDEC legal Counsel.
JEDEC standards and publications are designed to serve the public interest through eliminating
misunderstandings between manufacturers and purchasers, facilitating interchangeability and
improvement of products, and assisting the purchaser in selecting and obtaining with minimum
delay the proper product for use by those other than JEDEC members, whether the standard is to
be used either domestically or internationally.
JEDEC standards and publications are adopted without regard to whether or not their adoption
may involve patents or articles, materials, or processes. By such action JEDEC does not assume
any liability to any patent owner, nor does it assume any obligation whatever to parties adopting
the JEDEC standards or publications.
The information included in JEDEC standards and publications represents a sound approach to
product specification and application, principally from the solid state device manufacturer
viewpoint. Within the JEDEC organization, there are procedures whereby a JEDEC standard or
publication mya be further processed and ultimately become an ANSI standard.
No claims to be in conformance with this standard may be made unless all requirements stated in
the standard are met.
Inquiries, comments, and suggestions relative to the content of this JEDEC standard or
publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or
www.jedec.org.
Published by
©JEDEC Solid State Technology Association 2007
2500 Wilson Boulevard
Arlington, VA 22201-3834
This document may be downloaded free of charge, however JEDEC retains the
copyright on this material. By downloading this file the individual agrees not to
charge for or resell the resulting material.
Price: Please refer to the current
Catalog of JEDEC Engineering Standards and Publications online at
http://www.jedec.org/Catalog/catalog.cfm
Printed in the U.S.A.
All rights reserved
PLEASE!
DON’T VIOLATE
THE
LAW!
This document is copyrighted by JEDEC and may not be
reproduced without permission.
Organizations may obtain permission to reproduce a limited number of copies
through entering into a license agreement. For information, contact:
JEDEC Solid State Technology Association
2500 Wilson Boulevard
Arlington, Virginia 22201-3834
or call (703) 907-7559
JEDEC Standard No. 79-3A
Contents
i
1 Scope..........................................................................................................................................1
2 DDR3 SDRAM Package Pinout and Addressing ......................................................................3
2.1 DDR3 SDRAM x4 Ballout using MO-207 (Top view: see balls through package) ...... 3
2.2 DDR3 SDRAM x8 Ballout using MO-207 (Top view: see balls through package) ..... 4
2.3 DDR3 SDRAM x16 Ballout using MO-207 (Top view: see balls through package)..... 5
2.4 Stacked / dual-die DDR3 SDRAM x4 Ballout using MO-207 (Top view: see balls through
package).............................................................................................. 6
2.5 Stacked / dual-die DDR3 SDRAM x8 Ballout using MO-207 (Top view: see balls through
package).............................................................................................. 7
2.6 Stacked / dual-die DDR3 SDRAM x16 Ballout using MO-207 (Top view: see balls through
package).............................................................................................. 8
2.7 Pinout Description..............................................................................................................9
2.8 DDR3 SDRAM Addressing.............................................................................................11
2.8.1 512Mb .....................................................................................................................11
2.8.2 1Gb ...........................................................................................................................11
2.8.3 2Gb ..........................................................................................................................11
2.8.4 4Gb ..........................................................................................................................11
2.8.5 8Gb ..........................................................................................................................12
3 Functional Description.............................................................................................................13
3.1 Simplified State Diagram.................................................................................................13
3.2 Basic Functionality...........................................................................................................14
3.3 RESET and Initialization Procedure ................................................................................15
3.3.1 Power-up Initialization Sequence.............................................................................15
3.3.2 Reset Initialization with Stable Power .....................................................................17
3.4 Register Definition ...........................................................................................................18
3.4.1 Programming the Mode Registers............................................................................18
3.4.2 Mode Register MR0 .................................................................................................18
3.4.3 Mode Register MR1 .................................................................................................22
3.4.4 Mode Register MR2 .................................................................................................25
3.4.5 Mode Register MR3 .................................................................................................27
4 DDR3 SDRAM Command Description and Operation...........................................................29
4.1 Command Truth Table .....................................................................................................29
4.2 CKE Truth Table..............................................................................................................31
4.3 No OPeration (NOP) Command ......................................................................................32
4.4 Deselect Command ..........................................................................................................32
4.5 DLL-off Mode..................................................................................................................33
4.6 DLL on/off switching procedure......................................................................................34
4.6.1 DLL “on” to DLL “off” Procedure ..........................................................................34
4.6.2 DLL “off” to DLL “on” Procedure ..........................................................................35
4.7 Input clock frequency change ..........................................................................................36
4.8 Write Leveling .................................................................................................................38
4.8.1 DRAM setting for write leveling & DRAM termination function in that mode......38
4.8.2 Procedure Description ..............................................................................................39
4.8.3 Write Leveling Mode Exit........................................................................................41
4.9 Extended Temperature Usage ..........................................................................................42
剩余188页未读,继续阅读
SimonWang
- 粉丝: 2
- 资源: 9
上传资源 快速赚钱
- 我的内容管理 收起
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
会员权益专享
最新资源
- RTL8188FU-Linux-v5.7.4.2-36687.20200602.tar(20765).gz
- c++校园超市商品信息管理系统课程设计说明书(含源代码) (2).pdf
- 建筑供配电系统相关课件.pptx
- 企业管理规章制度及管理模式.doc
- vb打开摄像头.doc
- 云计算-可信计算中认证协议改进方案.pdf
- [详细完整版]单片机编程4.ppt
- c语言常用算法.pdf
- c++经典程序代码大全.pdf
- 单片机数字时钟资料.doc
- 11项目管理前沿1.0.pptx
- 基于ssm的“魅力”繁峙宣传网站的设计与实现论文.doc
- 智慧交通综合解决方案.pptx
- 建筑防潮设计-PowerPointPresentati.pptx
- SPC统计过程控制程序.pptx
- SPC统计方法基础知识.pptx
资源上传下载、课程学习等过程中有任何疑问或建议,欢迎提出宝贵意见哦~我们会及时处理!
点击此处反馈
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功
评论30