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RTL8214FC-VC-CG
INTEGRATED QUAD 10/100/1000M
ETHERNET TRANSCEIVER
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.2
13 November 2014
Track ID: JATR-8275-15
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211 Fax: +886-3-577-6047
www.realtek.com
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RTL8214FC-VC
Datasheet
Integrated Quad 10/100/1000M Ethernet Transceiver ii Track ID: JATR-8275-15 Rev. 1.2
COPYRIGHT
©2014 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
RTL8214FC-VC IC.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision Release Date Summary
1.0 2014/06/11 First release.
1.1 2014/07/21 Corrected minor typing errors.
Revised Table 3 RSGMII-Plus Pins, page 10.
Revised Table 4 QSGMII Pins, page 10.
Revised Table 7 Miscellaneous Pins, page 12.
Added section 6.9 1000Base-X/100Base-FX Interface Pins, page 14.
Revised section 9.3 Power Consumption, page 41.
1.2 2014/11/13 Revised Table 1, Pin Assignment Table, page 6 (EPAD GND pin).
Revised Figure 24 and Table 45, page 52.
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RTL8214FC-VC
Datasheet
Integrated Quad 10/100/1000M Ethernet Transceiver iii Track ID: JATR-8275-15 Rev. 1.2
Table of Contents
1. GENERAL DESCRIPTION..............................................................................................................................................1
2. FEATURES.........................................................................................................................................................................2
3. SYSTEM APPLICATIONS...............................................................................................................................................3
3.1. HIGH-PORT-DENSITY GIGABIT ETHERNET SWITCH; 1000BASE-T/ 1000BASE-X OR 100BASE-FX .............................3
4. BLOCK DIAGRAM...........................................................................................................................................................4
5. PIN ASSIGNMENTS .........................................................................................................................................................5
5.1. PIN ASSIGNMENTS .......................................................................................................................................................5
5.2. PACKAGE IDENTIFICATION...........................................................................................................................................5
5.3. PIN ASSIGNMENT TABLES ............................................................................................................................................6
6. PIN DESCRIPTIONS.........................................................................................................................................................9
6.1. MEDIA DEPENDENT INTERFACE PINS...........................................................................................................................9
6.2. RSGMII-PLUS PINS ...................................................................................................................................................10
6.3. QSGMII PINS ............................................................................................................................................................10
6.4. SERIAL LED PINS ......................................................................................................................................................10
6.5. CONFIGURATION PINS ................................................................................................................................................11
6.6. MISCELLANEOUS PINS ...............................................................................................................................................12
6.7. POWER AND GND PINS ..............................................................................................................................................13
6.8. TEST PINS ..................................................................................................................................................................14
6.9. 1000BASE-X/100BASE-FX INTERFACE PINS .............................................................................................................14
7. FUNCTION DESCRIPTION ..........................................................................................................................................16
7.1. MDI INTERFACE ........................................................................................................................................................16
7.2. 1000BASE-T TRANSMIT FUNCTION ...........................................................................................................................16
7.3. 1000BASE-T RECEIVE FUNCTION ..............................................................................................................................16
7.4. 100BASE-TX TRANSMIT FUNCTION...........................................................................................................................16
7.5. 100BASE-TX RECEIVE FUNCTION .............................................................................................................................17
7.6. 10BASE-T TRANSMIT FUNCTION ...............................................................................................................................17
7.7. 10BASE-T RECEIVE FUNCTION ..................................................................................................................................17
7.8. AUTO-NEGOTIATION FOR UTP ..................................................................................................................................17
7.9. CROSSOVER DETECTION AND AUTO CORRECTION.....................................................................................................18
7.10. POLARITY CORRECTION .............................................................................................................................................18
7.11. MDC/MDIO INTERFACE ...........................................................................................................................................19
7.12. REDUCED SERIAL GIGABIT MEDIA INDEPENDENT INTERFACE PLUS (RSGMII-PLUS)...............................................20
7.13. QUAD SERIAL GIGABIT MEDIA INDEPENDENT INTERFACE (QSGMII).......................................................................20
7.13.1. RSGMII-Plus Interface ....................................................................................................................................21
7.13.2. QSGMII Interface ............................................................................................................................................21
7.14. FIBER INTERFACE.......................................................................................................................................................22
7.14.1. Auto Sensing ....................................................................................................................................................22
7.14.2. FX_TX_DIS .....................................................................................................................................................22
7.14.3. Fiber Interface Application Circuit .................................................................................................................22
7.15. SERIAL LED...............................................................................................................................................................23
7.15.1. Port Status Indicator........................................................................................................................................23
7.15.2. LED Configuration ..........................................................................................................................................23
7.15.3. Serial LED Configuration Register .................................................................................................................26
7.15.4. Serial LED Timing Definitions ........................................................................................................................27
7.16. REALTEK CABLE TEST (RTCT) .................................................................................................................................27
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RTL8214FC-VC
Datasheet
Integrated Quad 10/100/1000M Ethernet Transceiver iv Track ID: JATR-8275-15 Rev. 1.2
7.17. GREEN ETHERNET......................................................................................................................................................28
7.17.1. Link-Up and Cable Length Power Saving .......................................................................................................28
7.17.2. Link-Down Power Saving ................................................................................................................................28
7.18. IEEE 802.3AZ ENERGY EFFICIENT ETHERNET (EEE) ................................................................................................28
7.19. INTERRUPT PIN FOR EXTERNAL CPU.........................................................................................................................28
7.20. REG.0.11 POWER DOWN MODE .................................................................................................................................28
7.21. REG.0.14 PHY DIGITAL LOOPBACK RETURN TO INTERNAL ......................................................................................29
8. REGISTER DESCRIPTIONS.........................................................................................................................................30
8.1. REGISTER 0: CONTROL...............................................................................................................................................31
8.2. REGISTER 1: STATUS..................................................................................................................................................32
8.3. REGISTER 2: PHY IDENTIFIER 1 .................................................................................................................................33
8.4. REGISTER 3: PHY IDENTIFIER 2 .................................................................................................................................33
8.5. REGISTER 4: AUTO-NEGOTIATION ADVERTISEMENT .................................................................................................33
8.6. REGISTER 4: 1000BASE-X AUTO-NEGOTIATION ADVERTISEMENT............................................................................34
8.7. REGISTER 5: AUTO-NEGOTIATION LINK PARTNER ABILITY.......................................................................................35
8.8. REGISTER 6: AUTO-NEGOTIATION EXPANSION ..........................................................................................................36
8.9. REGISTER 7: AUTO-NEGOTIATION NEXT PAGE TRANSMIT ........................................................................................36
8.10. REGISTER 8: AUTO-NEGOTIATION LINK PARTNER NEXT PAGE ABILITY ...................................................................37
8.11. REGISTER 9: 1000BASE-T CONTROL..........................................................................................................................37
8.12. REGISTER 10: 1000BASE-T STATUS...........................................................................................................................38
8.13. REGISTER 13: MMD ACCESS CONTROL REGISTER ....................................................................................................38
8.14. REGISTER 14: MMD ACCESS ADDRESS DATA REGISTER ..........................................................................................38
8.15. REGISTER 15: EXTENDED STATUS..............................................................................................................................39
9. ELECTRICAL CHARACTERISTICS ..........................................................................................................................40
9.1. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................40
9.2. OPERATING RANGE....................................................................................................................................................40
9.3. POWER CONSUMPTION...............................................................................................................................................41
9.4. IEEE 10/100/1000BASE-T SPECIFICATIONS ..............................................................................................................42
9.5. QSGMII CHARACTERISTICS ......................................................................................................................................43
9.5.1. QSGMII Differential Transmitter Characteristics ...............................................................................................43
9.5.2. QSGMII Differential Receiver Characteristics ....................................................................................................44
9.6. RSGMII-PLUS CHARACTERISTICS .............................................................................................................................45
9.6.1. RSGMII-Plus Differential Transmitter Characteristics........................................................................................45
9.6.2. RSGMII-Plus Differential Receiver Characteristics ............................................................................................46
9.7. 1000BASE-X CHARACTERISTICS................................................................................................................................47
9.7.1. 1000Base-X Differential Transmitter Characteristics..........................................................................................47
9.7.2. 1000Base-X Differential Receiver Characteristics...............................................................................................48
9.8. 100BASE-FX CHARACTERISTICS ...............................................................................................................................49
9.8.1. 100Base-FX Differential Transmitter Characteristics .........................................................................................49
9.8.2. 100Base-FX Differential Receiver Characteristics ..............................................................................................50
9.9. XTALI CLOCK CHARACTERISTICS ............................................................................................................................51
9.10. RESET CHARACTERISTICS ..........................................................................................................................................51
9.11. MDC/MDIO INTERFACE CHARACTERISTICS .............................................................................................................52
9.12. LED CHARACTERISTICS.............................................................................................................................................53
9.12.1. Serial LED Timing...........................................................................................................................................53
10. THERMAL CHARACTERISTICS ...........................................................................................................................54
10.1. ASSEMBLY DESCRIPTION ...........................................................................................................................................54
10.2. MATERIAL PROPERTIES..............................................................................................................................................54
10.3. SIMULATION CONDITIONS..........................................................................................................................................54
10.4. THERMAL PERFORMANCE OF E-PAD TQFP-176 ON PCB UNDER STILL AIR CONVENTION ........................................55
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RTL8214FC-VC
Datasheet
Integrated Quad 10/100/1000M Ethernet Transceiver v Track ID: JATR-8275-15 Rev. 1.2
11. MECHANICAL DIMENSIONS.................................................................................................................................56
11.1. TQFP-176 E-PAD PACKAGE .....................................................................................................................................56
11.2. MECHANICAL DIMENSIONS NOTES ............................................................................................................................56
12. ORDERING INFORMATION...................................................................................................................................57
List of Tables
TABLE 1. PIN ASSIGNMENT TABLE ................................................................................................................................................6
TABLE 2. MEDIA DEPENDENT INTERFACE PINS .............................................................................................................................9
TABLE 3. RSGMII-PLUS PINS .....................................................................................................................................................10
TABLE 4. QSGMII PINS...............................................................................................................................................................10
TABLE 5. PARALLEL LED PINS ...................................................................................................................................................10
TABLE 6. CONFIGURATION PINS ..................................................................................................................................................11
TABLE 7. MISCELLANEOUS PINS .................................................................................................................................................12
TABLE 8. POWER AND GND PINS ................................................................................................................................................13
TABLE 9. TEST PINS.....................................................................................................................................................................14
TABLE 10. 1000BASE-X/100BASE-FX INTERFACE PINS ...............................................................................................................14
TABLE 11. MEDIA DEPENDENT INTERFACE PIN MAPPING.............................................................................................................18
TABLE 12. SERIAL LED PER-LED CONTROL ................................................................................................................................23
TABLE 12. SERIAL LED MODE CONFIGURATION (PER-PORT 3 LEDS) .........................................................................................25
TABLE 13. SERIAL LED PER-LED CONTROL ................................................................................................................................26
TABLE 15. REGISTER DESCRIPTIONS .............................................................................................................................................30
TABLE 16. REGISTER 0: CONTROL ................................................................................................................................................31
TABLE 17. REGISTER 1: STATUS....................................................................................................................................................32
TABLE 18. REGISTER 2: PHY IDENTIFIER 1...................................................................................................................................33
TABLE 19. REGISTER 3: PHY IDENTIFIER 2...................................................................................................................................33
TABLE 20. REGISTER 4: AUTO-NEGOTIATION ADVERTISEMENT ...................................................................................................33
TABLE 21. REGISTER 4: 1000BASE-X AUTO-NEGOTIATION ADVERTISEMENT .............................................................................34
TABLE 22. REGISTER 5: AUTO-NEGOTIATION LINK PARTNER ABILITY ........................................................................................35
TABLE 23. REGISTER 6: AUTO-NEGOTIATION EXPANSION............................................................................................................36
TABLE 24. REGISTER 7: AUTO-NEGOTIATION NEXT PAGE TRANSMIT ..........................................................................................36
TABLE 25. REGISTER 8: AUTO-NEGOTIATION LINK PARTNER NEXT PAGE ABILITY .....................................................................37
TABLE 26. REGISTER 9: 1000BASE-T CONTROL ...........................................................................................................................37
TABLE 27. REGISTER 10: 1000BASE-T STATUS ............................................................................................................................38
TABLE 28. REGISTER 13: MMD ACCESS CONTROL REGISTER ......................................................................................................38
TABLE 29. REGISTER 14: MMD ACCESS ADDRESS DATA REGISTER ............................................................................................38
TABLE 30. REGISTER 15: EXTENDED STATUS ...............................................................................................................................39
TABLE 31. ABSOLUTE MAXIMUM RATINGS ..................................................................................................................................40
TABLE 32. OPERATING RANGE......................................................................................................................................................40
TABLE 33. POWER CONSUMPTION.................................................................................................................................................41
TABLE 34. IEEE 10/100/1000BASE-T SPECIFICATIONS ................................................................................................................42
TABLE 35. QSGMII DIFFERENTIAL TRANSMITTER CHARACTERISTICS.........................................................................................43
TABLE 36. QSGMII DIFFERENTIAL RECEIVER CHARACTERISTICS ...............................................................................................44
TABLE 37. RSGMII-PLUS DIFFERENTIAL TRANSMITTER CHARACTERISTICS ...............................................................................45
TABLE 38. RSGMII-PLUS DIFFERENTIAL RECEIVER CHARACTERISTICS ......................................................................................46
TABLE 39. 1000BASE-X DIFFERENTIAL TRANSMITTER CHARACTERISTICS ..................................................................................47
TABLE 40. RSGMII-PLUS DIFFERENTIAL RECEIVER CHARACTERISTICS ......................................................................................48
TABLE 41. 100BASE-FX DIFFERENTIAL TRANSMITTER CHARACTERISTICS ..................................................................................49
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