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Fast Fourier
Transform v9.1
LogiCORE IP Product Guide
Vivado Design Suite
PG109 June 17, 2020
Fast Fourier Transform v9.1 2
PG109 June 17, 2020 www.xilinx.com
Table of Contents
IP Facts
Chapter 1: Overview
Core Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Licensing and Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 2: Product Specification
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 3: Designing with the Core
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Event Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AXI4-Stream Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Chapter 4: Design Flow Steps
Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
System Generator for DSP Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Chapter 5: C Model
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Unpacking and Model Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Software Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
FFT C Model Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
C Model Example Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Compiling with the FFT C Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
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PG109 June 17, 2020 www.xilinx.com
FFT MATLAB Software MEX Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
MEX Function Example Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Modeling Multichannel FFTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Dependent Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Chapter 6: Test Bench
Demonstration Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Appendix A: Upgrading
Migrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Appendix B: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Simulation Debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
AXI4-Stream Interface Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Appendix C: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
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Fast Fourier Transform v9.1 4
PG109 June 17, 2020 www.xilinx.com Product Specification
Introduction
The Xilinx® LogiCORE™ IP Fast Fourier
Transform (FFT) core implements the
Cooley-Tukey FFT algorithm, a computationally
efficient method for calculating the Discrete
Fourier Transform (DFT).
Features
• Forward and inverse complex FFT, run time
configurable
• Transform sizes N = 2
m
, m = 3 – 16
• Data sample precision b
x
= 8 – 34
• Phase factor precision b
w
= 8 – 34
• Arithmetic types:
°
Unscaled (full-precision) fixed-point
°
Scaled fixed-point
°
Block floating-point
• Fixed-point or floating-point interface
• Rounding or truncation after the butterfly
• Block RAM or Distributed RAM for data and
phase-factor storage
• Optional run time configurable transform
point size
• Run time configurable scaling schedule for
scaled fixed-point cores
• Bit/digit reversed or natural output order
• Optional cyclic prefix insertion for digital
communications systems
• Four architectures offer a trade-off between
core size and transform time
• Bit accurate C model and MEX function for
system modeling available for download
IP Facts
LogiCORE IP Facts Table
Core Specifics
Supported
Device Family
(1)
UltraScale+™
UltraScale™
Zynq®-7000 SoC
7 Series
Supported User
Interfaces
AXI4-Stream
Resources
Performance and Resource Utilization web
page
Provided with Core
Design Files Encrypted RTL
Example Design Not Provided
Test Bench VHDL
Constraints File Not Provided
Simulation
Model
Encrypted VHDL
C Model
Supported
S/W Driver
N/A
Tested Design Flows
(2)
Design Entry
Vivado® Design Suite
System Generator for DSP
Simulation
For supported simulators, see the
Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado Synthesis
Support
Release Notes
and Known
Issues
Master Answer Record: 54501
All Vivado IP
Change Logs
Master Vivado IP Change Logs: 72775
Xilinx Support web page
Notes:
1. For a complete listing of supported devices, see the Vivado IP
catalog.
2. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide.
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PG109 June 17, 2020 www.xilinx.com
Chapter 1
Overview
Core Overview
The FFT core computes an N-point forward DFT or inverse DFT (IDFT) where N can be 2
m
,
m = 3–16.
For fixed-point inputs, the input data is a vector of N complex values represented as dual
b
x
-bit twos-complement numbers, that is, b
x
bits for each of the real and imaginary
components of the data sample, where b
x
is in the range 8 to 34 bits inclusive. Similarly, the
phase factors b
w
can be 8 to 34 bits wide.
For single-precision floating-point inputs, the input data is a vector of N complex values
represented as dual 32-bit floating-point numbers with the phase factors represented as
24- or 25-bit fixed-point numbers.
All memory is on-chip using either block RAM or distributed RAM. The N element output
vector is represented using b
y
bits for each of the real and imaginary components of the
output data. Input data is presented in natural order and the output data can be in either
natural or bit/digit reversed order. The complex nature of data input and output is intrinsic
to the FFT algorithm, not the implementation.
Three arithmetic options are available for computing the FFT:
• Full-precision unscaled arithmetic
• Scaled fixed-point, where you provide the scaling schedule
• Block floating-point (run time adjusted scaling)
The point size N, the choice of forward or inverse transform, the scaling schedule and the
cyclic prefix length are run time configurable. Transform type (forward or inverse), scaling
schedule and cyclic prefix length can be changed on a frame-by-frame basis. Changing the
point size resets the core.
Four architecture options are available: Pipelined Streaming I/O, Radix-4 Burst I/O, Radix-2
Burst I/O, and Radix-2 Lite Burst I/O. For detailed information about each architecture, see
Architecture Options.
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