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SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
This document contains information on a product under development. Solomon Systech reserves the right to change
or discontinue this product without notice.
http://www.solomon-systech.com
SSD2829
Rev 0.13
P 1/150
Sep 2016
Copyright
2016 Solomon Systech Limited
SSD2829
Product Preview
MIPI D-PHY Tx Bridge Chip
PN:Page 9
Symbol:Page 14-15
Decal:Page 149
Solomon Systech
Sep 2016
P 2/150
Rev 0.13
SSD2829
Appendix: IC Revision history of SSD2829 Specification
Version
Change Items Effective Date
0.10 1
st
Release 11-May-16
0.11 1. Section 5.2 Pin Assignment Table (Draft), pins 109 to 128 were amended
2. Modified operating temperature from 125oC to 85 oC
3. Modified MIPI D-Phy AC and DC Characteristic
4. Added back 8-bit MCU mode
5. Modified pin assignment table
6. Modified MIPI DPHY Lane and Polarity Swap table
7. Added description for compressed stream data
27-May-16
0.12 1. Modified max. PCLK value
2. Modified pin assignment table
16-Aug-16
0.13 1. Modified Table of MIPI packet ID
2. Modified AVDD_CDR pin description
3. Updated Command table
26
-Sep-16
SSD2829
Rev 0.13
P 3/150
Sep 2016
Solomon Systech
CONTENTS
1 GENERAL DESCRIPTION ....................................................................................................... 9
2 FEATURES................................................................................................................................... 9
3 ORDERING INFORMATION ................................................................................................... 9
4 BLOCK DIAGRAM .................................................................................................................. 10
5 FUNCTIONAL DESCRIPTION .............................................................................................. 11
5.1
RGB
I
NTERFACE
.................................................................................................................................................. 11
5.2
C
OMMAND
I
NTERFACE
........................................................................................................................................ 11
5.3
D
ATA
B
UFFER
...................................................................................................................................................... 11
5.4
C
OMMAND
B
UFFER
............................................................................................................................................. 11
5.5
MIPI
DSI-T
X
....................................................................................................................................................... 11
5.6
XTAL
OSC ......................................................................................................................................................... 13
5.7
PLL ..................................................................................................................................................................... 13
5.8
PMU .................................................................................................................................................................... 13
6 PIN ARRANGEMENT .............................................................................................................. 14
6.1
128
PINS
LQFP .................................................................................................................................................... 14
7 PIN DESCRIPTIONS ................................................................................................................ 16
7.1
P
OWER
S
UPPLY
P
IN
............................................................................................................................................. 16
7.2
MIPI
P
IN
.............................................................................................................................................................. 16
7.3
C
ONTROL
S
IGNAL
P
IN
......................................................................................................................................... 17
7.4
I
NTERFACE
L
OGIC
P
IN
......................................................................................................................................... 18
8 COMMAND TABLE ................................................................................................................. 19
8.1
L
OCAL
R
EGISTERS
(
NON
-APB)
D
ESCRIPTIONS
.................................................................................................... 19
8.1.1
RGB Interface Control Register 1 ............................................................................................................... 19
8.1.2
RGB Interface Control Register 2 ............................................................................................................... 20
8.1.3
RGB Interface Control Register 3 ............................................................................................................... 22
8.1.4
RGB Interface Control Register 4 ............................................................................................................... 23
8.1.5
RGB Interface Control Register 5 ............................................................................................................... 24
8.1.6
RGB Interface Control Register 6 ............................................................................................................... 25
8.1.7
Configuration Register ................................................................................................................................ 28
8.1.8
Virtual Channel Control Register ............................................................................................................... 31
8.1.9
PLL Control Register .................................................................................................................................. 33
8.1.10
PLL Configuration Register ........................................................................................................................ 34
8.1.11
Clock Control Register ............................................................................................................................... 35
8.1.12
Packet Size Control Register 1 .................................................................................................................... 36
8.1.13
Packet Size Control Register 2 .................................................................................................................... 38
8.1.14
Packet Size Control Register 3 .................................................................................................................... 39
8.1.15
Packet Drop Register .................................................................................................................................. 40
8.1.16
Operational Control Register ..................................................................................................................... 41
8.1.17
Maximum Return Size Register ................................................................................................................... 43
8.1.18
Return Data Count Register ........................................................................................................................ 44
8.1.19
Acknowledge Response Status Register ...................................................................................................... 45
8.1.20
Line Control Register .................................................................................................................................. 46
8.1.21
Interrupt Control Register .......................................................................................................................... 49
8.1.22
Interrupt Status Register ............................................................................................................................. 52
8.1.23
Error Status Register .................................................................................................................................. 56
8.1.24
Compressed Register .................................................................................................................................. 59
8.1.25
Delay Adjustment Register 1 ....................................................................................................................... 60
8.1.26
Delay Adjustment Register 2 ....................................................................................................................... 61
Solomon Systech
Sep 2016
P 4/150
Rev 0.13
SSD2829
8.1.27
Delay Adjustment Register 3 ....................................................................................................................... 62
8.1.28
Delay Adjustment Register 4 ....................................................................................................................... 63
8.1.29
Delay Adjustment Register 5 ....................................................................................................................... 64
8.1.30
Delay Adjustment Register 6 ....................................................................................................................... 65
8.1.31
HS TX Timer Register 1 .............................................................................................................................. 66
8.1.32
HS TX Timer Register 2 .............................................................................................................................. 67
8.1.33
TE Status Register ....................................................................................................................................... 68
8.1.34
SPI Read Register ....................................................................................................................................... 70
8.1.35
PLL Lock Register....................................................................................................................................... 71
8.1.36
Test Register ............................................................................................................................................... 72
8.1.37
TE Count Register ....................................................................................................................................... 74
8.1.38
Analog Control Register 1 .......................................................................................................................... 75
8.1.39
Interrupt Output Control Register .............................................................................................................. 77
8.1.40
RGB Interface Control Register 7 ............................................................................................................... 78
8.1.41
INOUT Configuration Control Register ..................................................................................................... 80
8.1.42
APB Write Register ..................................................................................................................................... 82
8.1.43
APB Read Register ...................................................................................................................................... 83
8.2
L
OCAL
(APB)
R
EGISTER
D
ESCRIPTIONS
.............................................................................................................. 84
8.2.1
SCM Registers Descriptions ....................................................................................................................... 85
8.2.1.1
SCM Miscellaneous Control Register ..................................................................................................... 85
8.2.1.2
SCM Scratch Register ............................................................................................................................. 87
8.2.2
Video BIST Register Descriptions ............................................................................................................... 88
8.2.2.1
Video BIST Register 0 ............................................................................................................................ 88
8.2.2.2
Video BIST Register 1 ............................................................................................................................ 89
8.2.2.3
Video BIST Register 2 ............................................................................................................................ 90
8.2.2.4
Video BIST Register 3 ............................................................................................................................ 91
8.2.2.5
Video BIST Register 4 ............................................................................................................................ 92
8.2.2.6
Video BIST Register 5 ............................................................................................................................ 93
8.2.2.7
Video BIST Register 6 ............................................................................................................................ 94
8.2.3
Pixel Peek Registers Descriptions .............................................................................................................. 95
8.2.3.1
Pixel Peek Register 0 .............................................................................................................................. 95
8.2.3.2
Pixel Peek Register 1 .............................................................................................................................. 96
8.2.3.3
Pixel Peek Register 2 .............................................................................................................................. 97
8.2.3.4
Pixel Peek Register 3 .............................................................................................................................. 98
9 MAXIMUM RATINGS ............................................................................................................. 99
10 DC OPERATING CONDITIONS ............................................................................................ 99
11 MIPI DPHY CHARACTERISTICS ...................................................................................... 100
11.1
MIPI
DPHY
HS
CHARACTERISTICS ........................................................................................................... 102
12 OPERATING MODE .............................................................................................................. 105
12.1
P
ROGRAMMING
M
ODEL
..................................................................................................................................... 105
12.1.1
Access Local (non-APB) Registers............................................................................................................ 106
12.1.2
Access Local (APB) Registers for Write ................................................................................................... 107
12.1.3
Access APB Registers for Read ................................................................................................................. 108
12.2
SPI
I
NTERFACE
.................................................................................................................................................. 110
12.2.1
SPI Interface 8-Bit 4 Wire ......................................................................................................................... 110
12.2.2
SPI Interface 8-Bit 3 Wire ......................................................................................................................... 112
12.2.3
SPI Interface 24-Bit 3 Wire ....................................................................................................................... 114
12.3
MCU
I
NTERFACE
............................................................................................................................................... 116
12.3.1
MCU Interface Type A, fixed E mode ....................................................................................................... 116
12.3.2
MCU Interface Type A, Clocked E mode .................................................................................................. 118
12.3.3
MCU Interface Type B .............................................................................................................................. 120
12.3.4
MCU Interface for MIPI Command Packet .............................................................................................. 122
12.3.5
MCU Interface for Local Registers ........................................................................................................... 123
12.4
RGB
I
NTERFACE
................................................................................................................................................ 124
12.5
V
IDEO
M
ODE
U
SE
C
ASES
.................................................................................................................................. 124
SSD2829
Rev 0.13
P 5/150
Sep 2016
Solomon Systech
12.5.1
RGB + SPI ................................................................................................................................................ 124
12.5.1.1
Interleaving Non-Video Packets with Video Packets ....................................................................... 127
12.5.2
Interrupt Operation ................................................................................................................................... 128
12.5.3
Internal Buffer Status ................................................................................................................................ 130
12.6
C
OMMAND
M
ODE
U
SE
C
ASES
........................................................................................................................... 131
12.6.1
Write Operation ........................................................................................................................................ 133
12.6.2
Read Operation ......................................................................................................................................... 134
12.7
V
IDEO TO
C
OMMAND
M
ODE CONVERSION
........................................................................................................ 135
12.8
S
TATE MACHINE OPERATION
.............................................................................................................................. 135
12.9
PHY
CONTROLLER
O
PERATION
......................................................................................................................... 136
12.10
PLL
C
ONFIGURATION
.................................................................................................................................... 136
12.11
C
LOCK
S
OURCE
E
XAMPLE
............................................................................................................................. 137
12.12
A
CKNOWLEDGEMENT
O
PERATION
................................................................................................................. 138
12.13
T
EARING
E
FFECT
(TE)
O
PERATION
............................................................................................................... 140
12.13.1
Using IO Pins ........................................................................................................................................ 140
12.13.2
Using MIPI Escape Mode ..................................................................................................................... 141
12.14
C
ONTENTION
D
ETECTION AND
T
IMER
O
PERATION
........................................................................................ 141
12.15
V
IDEO
BIST .................................................................................................................................................. 142
12.16
P
IXEL
P
EEK
.................................................................................................................................................... 147
12.17
I
MAGE
F
LIPPING
(H
ORIZONTAL
) .................................................................................................................... 148
13 PACKAGE INFORMATION ................................................................................................. 149
13.1
QFP
128
PINS
(14
MM X
14
MM
) .......................................................................................................................... 149
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