联想thinkpadT470S笔记本电脑电路原理图_联想T470关闭触摸板快捷方式

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T470S

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D D

C C

B B

A A

Thorpe-2 TBT Logic Schematics

1.TITLE PAGE

2.EC HISTORY

3.CPU(1/16) : DDI/EDP

6.CPU(4/16) : MISC/JTAG

4.CPU(2/16) : DDR CHANNEL-A

5.CPU(3/16) : DDR CHANNEL-B

9.CPU(7/16) : AUDIO/SDXC

12.CPU(10/16) : CLOCK SIGNALS

7.CPU(5/16) : LPC/SPI/SMBUS/C-LINK

13.CPU(11/16) : SYSTEM PM

19.XDP CONNECTOR

11.CPU(9/16) : CSI-2/EMMC

8.CPU(6/16) : LPSS/ISH

10.CPU(8/16) : PCIE/USB/SATA

14.CPU(12/16) : CPU POWER (1/2)

15.CPU(13/16) : CPU POWER (2/2)

16.CPU(14/16) : PCH POWER

17.CPU(15/16) : GND

18.CPU(16/16) : CFG/RESERVED

29.DDI DEMUX/HDMI LEVEL SHIFTER

30.HDMI CONNECTOR

27.BLANK

20.RTC BATTERY

31.M.2 SATA/PCIE SSD CARD SLOT

32.USB POWER/CONN

50.AUDIO ALC3268

51.AUDIO HP JACK DETECT

52.AUDIO JACK SENSE

53.BLANK

54.AUDIO SPEAKER

55.AUDIO BEEP

34.GBE JACKSONVILLE

35.GBE LAN SWITCH

37.RJ45 CONNECTOR

46.PCIE M.2 (NGFF) CARD SLOT

47.SD/AUDIO CONNECTOR I/F

48.BLANK

49.BLANK

21.SPI FLASH

57.DOCKING CONNECTOR

58.MEC1653(1/3)

59.MEC1653(2/3)

61.KEYBOARD/TRACK POINT

62.TOUCH PAD/FPR/SCR

63.FAN CONNECTOR

64.APS G-SENSOR

65.DISCRETE TPM 2.0

66.SMBUS SWITCH/LPC DEBUG PORT

69.DC-IN

70.BATTERY INPUT

72.CHARGER SELECTOR

73.BLANK

74.DC/DC VCC5M/VCC3M (TPS51285B-1)

76.DC/DC VCCCPUCORE(NCP81382)

THP2 D-0

VER 0.01

Oct/26/2016

BASE LOGIC :

thp2_sitr_lcfc_20161014

75.DC/DC IMVP8 CONTROLLER(NCP81218)

80.DC/DC VCCCPUIO(NB682)

85.DC/DC VCC2R5A(TLV62080)

83.DC/DC VCC1R2A(TPS51716RUKR)

84.BLANK

98.BLANK

89.BLANK

94.LOAD SW LAN

96.LOAD SW B

99.PTH FOR SCREW HOLES

97.LOAD SW WWAN & WLAN

60.MEC1653(3/3)

67.THINK ENGINE-2(1/2)

68.THINK ENGINE-2(2/2)

26.LCD/USB/LID/MIC/CAMERA/PWR SW

93.LOAD SW PCH SUS/TRACK POINT

77.DC/DC VCCGFXCORE_I(NCP81382)

78.DC/DC VCCSA(NCP81380)

79.BLANK

81.DC/DC VCC1R0_SUS(BD91364BMUU)

88.BLANK

87.DC/DC VCCPCHCORE(NB695)

82.LOAD SW VCCST & VCCSTG

56.BLANK

33.BLANK

28.BLANK

25.DDR4 SO DIMM CHANNEL-B (2/2)

24.DDR4 SO DIMM CHANNEL-B (1/2)

42.BLANK

43.BLANK

44.BLANK

38.BLANK

39.BLANK

40.BLANK

41.BLANK

45.BLANK

90.BLANK

91.BLANK

92.BLANK

95.BLANK

22.DDR4 BASE MEMORY CH-A (1/2)

23.DDR4 BASE MEMORY CH-A (2/2)

86.DC/DC VCC1R8_SUS(BU90104GWZ)

100. ALPINE RIDGE LP(1/2)

101. ALPINE RIDGE LP(2/2)

102. TBT PORT

36.GBE MAGNETICS

71.BATTERY CHARGER(BQ25700) 103. USB TYPE-C PROTOCTOR

Size

Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Deciphered Date

Title

Thorpe-2 UMA

0.01

TITLE PAGE

Custom

1 103

Wednesday, October 26, 2016

2012/07/01

2014/07/01

Size

Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Deciphered Date

Title

Thorpe-2 UMA

0.01

TITLE PAGE

Custom

1 103

Wednesday, October 26, 2016

2012/07/01

2014/07/01

Size

Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Deciphered Date

Title

Thorpe-2 UMA

0.01

TITLE PAGE

Custom

1 103

Wednesday, October 26, 2016

2012/07/01

2014/07/01

D D

C C

B B

A A

EC HISTORY

CS15 THP2 D-0

(BASE LOGIC : thp2_sitr_lcfc_20161014)

Size [mm]

TABLE: Chip Part Dimension

mm Size Code Inch Size Code

0.40 x 0.20

0.60 x 0.30

1.00 x 0.50

1.60 x 0.80

2.00 x 1.25

2.00 x 1.60

2.50 x 2.00

3.20 x 1.60

3.20 x 2.50

4.50 x 1.60

4.50 x 2.50

4.50 x 3.20

5.00 x 2.50

6.40 x 3.20

0402

0603

1005

1608

2125

2016

2520

3216

3225

4516

4525

4532

5025

6432

01005

0201

0402

0603

0805

0806

1008

1206

1210

1806

1810

1812

2010

2512

LOGIC

TABLE: Chip Capacitor Tolerance

Tole ra nc e Code

+/-0.25pF

+/-0.5pF

+/-5%

+/-10%

+/-20%

+80/-20%

TABLE: Chip Capacitor Thermal Characteristics

Code

-55 to 150degC

-55 to 125degC

+/-30ppm/degC

+/-15%

+/-22%

+/-15%

-55 to 125degC

-55 to 105degC

-55 to 85degC

NPO

C0G

X7R

X6S

X5R

VER.0.01 10/26/2016 APPLIED Power ECR10192016 / EC10242016

Size

Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Deciphered Date

Title

Thorpe-2 UMA

0.01

EC HISTORY

Custom

2 103

Wednesday, October 26, 2016

2012/07/01

2014/07/01

Size

Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Deciphered Date

Title

Thorpe-2 UMA

0.01

EC HISTORY

Custom

2 103

Wednesday, October 26, 2016

2012/07/01

2014/07/01

Size

Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Deciphered Date

Title

Thorpe-2 UMA

0.01

EC HISTORY

Custom

2 103

Wednesday, October 26, 2016

2012/07/01

2014/07/01

D D

C C

B B

A A

TABLE : Functional Strap

DDPB_CTRLDATA

HIGH

LOW

DDPC_CTRLDATA

HIGH

Port B is detected.

LOW

Port B is not detected.

Port C is not detected.

Port C is detected.

EDP_COMP

EDP_AUXN

EDP_AUXP

EDP_TXN0

EDP_TXP0

EDP_TXN1

EDP_TXP1

DDIP1_0N

DDIP1_0P

DDIP1_1N

DDIP1_1P

DDIP1_2N

DDIP1_2P

DDIP1_3N

DDIP1_3P

DDIP2_0N

DDIP2_0P

DDIP2_1N

DDIP2_1P

DDIP2_2N

DDIP2_2P

DDIP2_3N

DDIP2_3P

EDP_TXP2

EDP_TXN2

EDP_TXP3

EDP_TXN3

DDIP1_AUXP

DDIP2_AUXP

DDIP1_AUXN

DDIP2_AUXN

DDIP2_CTRLDATA

DDIP2_CTRLCLK

DDIP2_HPD

DDIP1_HPD

EDP_TXP1 26

EDP_TXN1 26

EDP_TXP0 26

EDP_TXN0 26

EDP_AUXP 26

EDP_AUXN 26

DDIP1_0N100

DDIP1_0P100

DDIP1_1N100

DDIP1_1P100

DDIP1_2P100

DDIP1_2N100

DDIP1_3N100

DDIP1_3P100

DDIP2_2P29

DDIP2_2N29

DDIP2_3N29

DDIP2_3P29

DDIP2_0P29

DDIP2_0N29

DDIP2_1N29

DDIP2_1P29

EDP_TXN2 26

EDP_TXP2 26

EDP_TXN3 26

EDP_TXP3 26

DDIP2_CTRLCLK29

DDIP2_CTRLDATA29

DDIP1_AUXN 100

DDIP1_AUXP 100

DDIP2_AUXN 29

DDIP2_AUXP 29

DDIP1_HPD 100

DDIP2_HPD 29

EDP_HPD 26

VGA_BLON 58

PANEL_BKLT_CTRL 26

PANEL_POWER_ON 68

VCCCPUIOVCC3_SUS

Size

Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Deciphered Date

Title

Thorpe-2 UMA

0.01

CPU(1/16) : DDI/EDP

Custom

3 103

Wednesday, October 26, 2016

2012/07/01

2014/07/01

Size

Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Deciphered Date

Title

Thorpe-2 UMA

0.01

CPU(1/16) : DDI/EDP

Custom

3 103

Wednesday, October 26, 2016

2012/07/01

2014/07/01

Size

Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Deciphered Date

Title

Thorpe-2 UMA

0.01

CPU(1/16) : DDI/EDP

Custom

3 103

Wednesday, October 26, 2016

2012/07/01

2014/07/01

SKL_ULT

EDP

DISPLAY SIDEBANDS

DDI

1 OF 20

U58A

Kaby lake-U_BGA1356

DDI1_AUXN

G50

DDI1_AUXP

F50

DDI1_TXN[0]

E55

DDI1_TXN[1]

E58

DDI1_TXN[2]

F53

DDI1_TXN[3]

F56

DDI1_TXP[0]

F55

DDI1_TXP[1]

F58

DDI1_TXP[2]

G53

DDI1_TXP[3]

G56

DDI2_AUXN

E48

DDI2_AUXP

F48

DDI2_TXN[0]

C50

DDI2_TXN[1]

C52

DDI2_TXN[2]

A50

DDI2_TXN[3]

D51

DDI2_TXP[0]

D50

DDI2_TXP[1]

D52

DDI2_TXP[2]

B50

DDI2_TXP[3]

C51

DDI3_AUXN

G46

DDI3_AUXP

F46

EDP_RCOMP

E52

EDP_AUXN

E45

EDP_AUXP

F45

EDP_DISP_UTIL

B52

EDP_TXN[0]

C47

EDP_TXN[1]

D46

EDP_TXN[2]

A45

EDP_TXN[3]

A47

EDP_TXP[0]

C46

EDP_TXP[1]

C45

EDP_TXP[2]

B45

EDP_TXP[3]

B47

GPP_E13/DDPB_HPD0

GPP_E14/DDPC_HPD1

GPP_E15/DDPD_HPD2

GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

L10

GPP_E18/DDPB_CTRLCLK

L13

GPP_E19/DDPB_CTRLDATA

L12

GPP_E20/DDPC_CTRLCLK

GPP_E21/DDPC_CTRLDATA

GPP_E22/DDPD_CTRLCLK

N11

GPP_E23/DDPD_CTRLDATA

N12

EDP_BKLTCTL

R11

EDP_BKLTEN

R12

EDP_VDDEN

U13

R433

100K_0201_5%

1 2

24.9_0201_1%

100K_0201_5%

1 2

R10261

100K_0201_5%

1 2

R10227

2.2K_0201_5%

R10234

100K_0201_5%

1 2

R138

100K_0201_5%

1 2

D D

C C

B B

A A

Block 0

DDR0_DQ[0]

DDR0_DQ[1]

DDR0_DQ[2]

DDR0_DQ[3]

DDR0_DQ[4]

DDR0_DQ[5]

DDR0_DQ[6]

DDR0_DQ[7]

DDR0_DQ[8]

DDR0_DQ[9]

DDR0_DQ[10]

DDR0_DQ[11]

DDR0_DQ[12]

DDR0_DQ[13]

DDR0_DQ[14]

DDR0_DQ[15]

Non-Interleave

Block 2

Block 4

Block 6

Interleave

DDR0_DQ[0]

DDR0_DQ[1]

DDR0_DQ[2]

DDR0_DQ[3]

DDR0_DQ[4]

DDR0_DQ[5]

DDR0_DQ[6]

DDR0_DQ[7]

DDR0_DQ[8]

DDR0_DQ[9]

DDR0_DQ[10]

DDR0_DQ[11]

DDR0_DQ[12]

DDR0_DQ[13]

DDR0_DQ[14]

DDR0_DQ[15]

AL71

AL68

AN68

AN69

AL70

AL69

AN70

AN71

AR70

AR68

AU71

AU68

AR71

AR69

AU70

AU69

BB65

AW65

AW63

AY 6 3

BA65

AY 6 5

BA63

BB63

BA61

AW61

BB59

AW59

BB61

AY 6 1

BA59

AY 5 9

AY39

AW39

AY 3 7

AW37

BB39

BA39

BA37

BB37

AY 3 5

AW35

AY 3 3

AW33

BB35

BA35

BA33

BB33

AY31

AW31

AY 2 9

AW29

BB31

BA31

BA29

BB29

AY 2 7

AW27

AY 2 5

AW25

BB27

BA27

BA25

BB25

DDR0_DQ[16]

DDR0_DQ[17]

DDR0_DQ[18]

DDR0_DQ[19]

DDR0_DQ[20]

DDR0_DQ[21]

DDR0_DQ[22]

DDR0_DQ[23]

DDR0_DQ[24]

DDR0_DQ[25]

DDR0_DQ[26]

DDR0_DQ[27]

DDR0_DQ[28]

DDR0_DQ[29]

DDR0_DQ[30]

DDR0_DQ[31]

DDR0_DQ[48]

DDR0_DQ[49]

DDR0_DQ[50]

DDR0_DQ[51]

DDR0_DQ[52]

DDR0_DQ[53]

DDR0_DQ[54]

DDR0_DQ[55]

DDR0_DQ[56]

DDR0_DQ[57]

DDR0_DQ[58]

DDR0_DQ[59]

DDR0_DQ[60]

DDR0_DQ[61]

DDR0_DQ[62]

DDR0_DQ[63]

LOGIC

Interleave

Non-Interleave

AM70

AM69

AT69

AT70

BA64

AY 64

AY 60

BA60

BA38

AY 38

AY 34

BA34

BA30

AY 30

AY 26

BA26

Block 0

Block 2

Block 4

Block 6

DDR0_DQSN[0]

DDR0_DQSP[0]

DDR0_DQSN[1]

DDR0_DQSP[1]

DDR0_DQSN[0]

DDR0_DQSP[0]

DDR0_DQSN[1]

DDR0_DQSP[1]

DDR0_DQSN[4]

DDR0_DQSP[4]

DDR0_DQSN[5]

DDR0_DQSP[5]

DDR0_DQSN[2]

DDR0_DQSP[2]

DDR0_DQSN[3]

DDR0_DQSP[3]

DDR0_DQSN[4]

DDR0_DQSP[4]

DDR0_DQSN[5]

DDR0_DQSP[5]

DDR1_DQSN[0]

DDR1_DQSP[0]

DDR1_DQSN[1]

DDR1_DQSP[1]

DDR1_DQSN[4]

DDR1_DQSP[4]

DDR1_DQSN[5]

DDR1_DQSP[5]

DDR0_DQSN[6]

DDR0_DQSP[6]

DDR0_DQSN[7]

DDR0_DQSP[7]

LOGIC

BA51

BB54

BA52

AY 52

AW52

AY 5 5

AW54

BA54

BA55

AY 5 4

DDR0_CAA[0]

DDR0_CAA[1]

DDR0_CAA[2]

DDR0_CAA[3]

DDR0_CAA[4]

DDR0_CAA[5]

DDR0_CAA[6]

DDR0_CAA[7]

DDR0_CAA[8]

DDR0_CAA[9]

LOGIC

DDR0_MA[5]

DDR0_MA[9]

DDR0_MA[6]

DDR0_MA[8]

DDR0_MA[7]

DDR0_BA[2]

DDR0_MA[12]

DDR0_MA[11]

DDR0_MA[15]

DDR0_MA[14]

DDR0_MA[5]

DDR0_MA[9]

DDR0_MA[6]

DDR0_MA[8]

DDR0_MA[7]

DDR0_BG[0]

DDR0_MA[12]

DDR0_MA[11]

DDR0_ACT#

DDR0_BG[1]

AU46

AU48

AT46

AU50

AU52

AY 51

AT48

AT50

BB50

AY 50

BA50

BB52

DDR3L LPDDR3 DDR4

DDR0_MA[13]

DDR0_CAS#

DDR0_WE#

DDR0_RAS#

DDR0_BA[0]

DDR0_MA[2]

DDR0_BA[1]

DDR0_MA[10]

DDR0_MA[1]

DDR0_MA[0]

DDR0_MA[3]

DDR0_MA[4]

DDR0_CAB[0]

DDR0_CAB[1]

DDR0_CAB[2]

DDR0_CAB[3]

DDR0_CAB[4]

DDR0_CAB[5]

DDR0_CAB[6]

DDR0_CAB[7]

DDR0_CAB[8]

DDR0_CAB[9]

Not Used

DDR0_MA[13]

DDR0_MA[15]

DDR0_MA[14]

DDR0_MA[16]

DDR0_BA[0]

DDR0_MA[2]

DDR0_BA[1]

DDR0_MA[10]

DDR0_MA[1]

DDR0_MA[0]

DDR0_MA[3]

DDR0_MA[4]

DDR0_DQ[32]

DDR0_DQ[33]

DDR0_DQ[34]

DDR0_DQ[35]

DDR0_DQ[36]

DDR0_DQ[37]

DDR0_DQ[38]

DDR0_DQ[39]

DDR0_DQ[40]

DDR0_DQ[41]

DDR0_DQ[42]

DDR0_DQ[43]

DDR0_DQ[44]

DDR0_DQ[45]

DDR0_DQ[46]

DDR0_DQ[47]

DDR0_DQ[32]

DDR0_DQ[33]

DDR0_DQ[34]

DDR0_DQ[35]

DDR0_DQ[36]

DDR0_DQ[37]

DDR0_DQ[38]

DDR0_DQ[39]

DDR0_DQ[40]

DDR0_DQ[41]

DDR0_DQ[42]

DDR0_DQ[43]

DDR0_DQ[44]

DDR0_DQ[45]

DDR0_DQ[46]

DDR0_DQ[47]

DDR1_DQ[0]

DDR1_DQ[1]

DDR1_DQ[2]

DDR1_DQ[3]

DDR1_DQ[4]

DDR1_DQ[5]

DDR1_DQ[6]

DDR1_DQ[7]

DDR1_DQ[8]

DDR1_DQ[9]

DDR1_DQ[10]

DDR1_DQ[11]

DDR1_DQ[12]

DDR1_DQ[13]

DDR1_DQ[14]

DDR1_DQ[15]

DDR1_DQ[32]

DDR1_DQ[33]

DDR1_DQ[34]

DDR1_DQ[35]

DDR1_DQ[36]

DDR1_DQ[37]

DDR1_DQ[38]

DDR1_DQ[39]

DDR1_DQ[40]

DDR1_DQ[41]

DDR1_DQ[42]

DDR1_DQ[43]

DDR1_DQ[44]

DDR1_DQ[45]

DDR1_DQ[46]

DDR1_DQ[47]

TABL E

M_A_DQ4

M_A_DQ0

M_A_DQ1

M_A_DQ7

M_A_DQ6

M_A_DQ2

M_A_DQ3

M_A_DQ5

M_A_DQ12

M_A_DQ14

M_A_DQ11

M_A_DQ9

M_A_DQ10

M_A_DQ8

M_A_DQ15

M_A_DQ13

M_A_DQ20

M_A_DQ16

M_A_DQ17

M_A_DQ23

M_A_DQ22

M_A_DQ18

M_A_DQ19

M_A_DQ21

M_A_DQ28

M_A_DQ24

M_A_DQ25

M_A_DQ31

M_A_DQ26

M_A_DQ30

M_A_DQ27

M_A_DQ29

M_A_DQ32

M_A_DQ38

M_A_DQ33

M_A_DQ39

M_A_DQ36

M_A_DQ34

M_A_DQ37

M_A_DQ35

M_A_DQ46

M_A_DQ44

M_A_DQ45

M_A_DQ41

M_A_DQ40

M_A_DQ42

M_A_DQ47

M_A_DQ43

M_A_DQ48

M_A_DQ50

M_A_DQ51

M_A_DQ55

M_A_DQ54

M_A_DQ52

M_A_DQ53

M_A_DQ49

M_A_DQ62

M_A_DQ56

M_A_DQ57

M_A_DQ61

M_A_DQ58

M_A_DQ60

M_A_DQ59

M_A_DQ63

-M_A_DQS0

-M_A_DQS1

-M_A_DQS2

-M_A_DQS3

-M_A_DQS4

-M_A_DQS5

-M_A_DQS6

-M_A_DQS7

M_A_DQS0

M_A_DQS1

M_A_DQS2

M_A_DQS3

M_A_DQS4

M_A_DQS5

M_A_DQS6

M_A_DQS7

M_A_A0

M_A_A1

M_A_A2

M_A_A3

M_A_A4

M_A_A5

M_A_A6

M_A_A7

M_A_A8

M_A_A9

M_A_A10

M_A_A11

M_A_A12

M_A_A13

M_A_BG1

-M_A_ACT

M_A_BS1

M_A_BG0

M_A_BS0

M_A_A15

M_A_A16

M_A_A14

-M_A_CS0

-M_A_DDRCLK0_1066M

M_A_CKE0

M_A_DDRCLK0_1066M

DDR_VTT_PG_CTRL

DDR_PG_CTRL

M_A_ODT0

-M_A_ALERT

M_A_PARITY

-M_A_DQS[7:0] 22

M_A_DQS[7:0] 22

M_A_VREF_CA_CPU 23

DDR_VTT_PG_CTRL 83

-M_A_DDRCLK0_1066M 22,23

M_A_DDRCLK0_1066M 22,23

M_A_CKE0 22,23

-M_A_CS0 22,23

M_A_BG0 22,23

M_A_BS0 22,23

M_A_BS1 22,23

M_A_A[16:0] 22,23

M_A_DQ[63:0]22

M_A_ODT0 22,23

-M_A_ACT 22,23

M_A_BG1 22

-M_A_ALERT 22,23

M_A_PARITY 22,23

M_B_VREF_CA_CPU 24

VCC3M

VCC1R2A

Size

Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Deciphered Date

Title

Thorpe-2 UMA

0.01

CPU(2/16) : DDR CHANNEL-A

Custom

4 103

Wednesday, October 26, 2016

2012/07/01

2014/07/01

Size

Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Deciphered Date

Title

Thorpe-2 UMA

0.01

CPU(2/16) : DDR CHANNEL-A

Custom

4 103

Wednesday, October 26, 2016

2012/07/01

2014/07/01

Size

Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Deciphered Date

Title

Thorpe-2 UMA

0.01

CPU(2/16) : DDR CHANNEL-A

Custom

4 103

Wednesday, October 26, 2016

2012/07/01

2014/07/01

Q170

DTC115TMT2L_VMT3

R1838

100K_0201_5%

1 2

R1858

10K_0201_5%

1 2

SKL_ULT

DDR CH - A

2 OF 20

U58B

Kaby lake-U_BGA1356

DDR_VREF_CA

AY67

DDR0_VREF_DQ

AY68

DDR1_VREF_DQ

BA67

DDR_VTT_CNTL

AW67

DDR0_ALERT#

AW50

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

AU52

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

AT48

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

AY55

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

AU48

DDR0_CKE[0]

BA56

DDR0_CKE[1]

BB56

DDR0_CKE[2]

AW56

DDR0_CKE[3]

AY56

DDR0_CKN[0]

AU53

DDR0_CKN[1]

AU55

DDR0_CKP[0]

AT53

DDR0_CKP[1]

AT55

DDR0_CS#[0]

AU45

DDR0_CS#[1]

AU43

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

AY50

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]

BB50

DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

AT50

DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

BA54

DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]

AW54

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

AU46

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

AY54

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#

BA55

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

AY51

DDR0_MA[3]

BA50

DDR0_MA[4]

BB52

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]

BA51

DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]

BA52

DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

AW52

DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]

AY52

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]

BB54

DDR0_ODT[0]

AT45

DDR0_ODT[1]

AT43

DDR0_PAR

AT52

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

AU50

DDR0_W E#/DDR0_CAB[2]/DDR0_MA[14]

AT46

DDR0_DQ[0]

AL71

DDR0_DQ[1]

AL68

DDR0_DQ[2]

AN68

DDR0_DQ[3]

AN69

DDR0_DQ[4]

AL70

DDR0_DQ[5]

AL69

DDR0_DQ[6]

AN70

DDR0_DQ[7]

AN71

DDR0_DQ[8]

AR70

DDR0_DQ[9]

AR68

DDR0_DQ[10]

AU71

DDR0_DQ[11]

AU68

DDR0_DQ[12]

AR71

DDR0_DQ[13]

AR69

DDR0_DQ[14]

AU70

DDR0_DQ[15]

AU69

DDR0_DQ[16]/DDR0_DQ[32]

BB65

DDR0_DQ[17]/DDR0_DQ[33]

AW65

DDR0_DQ[18]/DDR0_DQ[34]

AW63

DDR0_DQ[19]/DDR0_DQ[35]

AY63

DDR0_DQ[20]/DDR0_DQ[36]

BA65

DDR0_DQ[21]/DDR0_DQ[37]

AY65

DDR0_DQ[22]/DDR0_DQ[38]

BA63

DDR0_DQ[23]/DDR0_DQ[39]

BB63

DDR0_DQ[24]/DDR0_DQ[40]

BA61

DDR0_DQ[25]/DDR0_DQ[41]

AW61

DDR0_DQ[26]/DDR0_DQ[42]

BB59

DDR0_DQ[27]/DDR0_DQ[43]

AW59

DDR0_DQ[28]/DDR0_DQ[44]

BB61

DDR0_DQ[29]/DDR0_DQ[45]

AY61

DDR0_DQ[30]/DDR0_DQ[46]

BA59

DDR0_DQ[31]/DDR0_DQ[47]

AY59

DDR0_DQ[32]/DDR1_DQ[0]

AY39

DDR0_DQ[33]/DDR1_DQ[1]

AW39

DDR0_DQ[34]/DDR1_DQ[2]

AY37

DDR0_DQ[35]/DDR1_DQ[3]

AW37

DDR0_DQ[36]/DDR1_DQ[4]

BB39

DDR0_DQ[37]/DDR1_DQ[5]

BA39

DDR0_DQ[38]/DDR1_DQ[6]

BA37

DDR0_DQ[39]/DDR1_DQ[7]

BB37

DDR0_DQ[40]/DDR1_DQ[8]

AY35

DDR0_DQ[41]/DDR1_DQ[9]

AW35

DDR0_DQ[42]/DDR1_DQ[10]

AY33

DDR0_DQ[43]/DDR1_DQ[11]

AW33

DDR0_DQ[44]/DDR1_DQ[12]

BB35

DDR0_DQ[45]/DDR1_DQ[13]

BA35

DDR0_DQ[46]/DDR1_DQ[14]

BA33

DDR0_DQ[47]/DDR1_DQ[15]

BB33

DDR0_DQ[48]/DDR1_DQ[32]

AY31

DDR0_DQ[49]/DDR1_DQ[33]

AW31

DDR0_DQ[50]/DDR1_DQ[34]

AY29

DDR0_DQ[51]/DDR1_DQ[35]

AW29

DDR0_DQ[52]/DDR1_DQ[36]

BB31

DDR0_DQ[53]/DDR1_DQ[37]

BA31

DDR0_DQ[54]/DDR1_DQ[38]

BA29

DDR0_DQ[55]/DDR1_DQ[39]

BB29

DDR0_DQ[56]/DDR1_DQ[40]

AY27

DDR0_DQ[57]/DDR1_DQ[41]

AW27

DDR0_DQ[58]/DDR1_DQ[42]

AY25

DDR0_DQ[59]/DDR1_DQ[43]

AW25

DDR0_DQ[60]/DDR1_DQ[44]

BB27

DDR0_DQ[61]/DDR1_DQ[45]

BA27

DDR0_DQ[62]/DDR1_DQ[46]

BA25

DDR0_DQ[63]/DDR1_DQ[47]

BB25

DDR0_DQSN[0]

AM70

DDR0_DQSN[1]

AT69

DDR0_DQSN[2]/DDR0_DQSN[4]

BA64

DDR0_DQSN[3]/DDR0_DQSN[5]

AY60

DDR0_DQSN[4]/DDR1_DQSN[0]

BA38

DDR0_DQSN[5]/DDR1_DQSN[1]

AY34

DDR0_DQSN[6]/DDR1_DQSN[4]

BA30

DDR0_DQSN[7]/DDR1_DQSN[5]

AY26

DDR0_DQSP[0]

AM69

DDR0_DQSP[1]

AT70

DDR0_DQSP[2]/DDR0_DQSP[4]

AY64

DDR0_DQSP[3]/DDR0_DQSP[5]

BA60

DDR0_DQSP[4]/DDR1_DQSP[0]

AY38

DDR0_DQSP[5]/DDR1_DQSP[1]

BA34

DDR0_DQSP[6]/DDR1_DQSP[4]

AY30

DDR0_DQSP[7]/DDR1_DQSP[5]

BA26

D D

C C

B B

A A

Block 5

Block 7

Interleave

AF65

AF64

AK65

AK64

AF66

AF67

AK67

AK66

AF70

AF68

AH71

AH68

AF71

AF69

AH70

AH69

AT66

AU66

AP65

AN65

AN66

AP66

AT65

AU65

AT61

AU61

AP60

AN60

AN61

AP61

AT60

AU60

AU40

AT40

AT37

AU37

AR40

AP40

AP37

AR37

AT33

AU33

AU30

AT30

AR33

AP33

AR30

AP30

AU27

AT27

AT25

AU25

AP27

AN27

AN25

AP25

AT22

AU22

AU21

AT21

AN22

AP22

AP21

AN21

DDR1_DQ[16]

DDR1_DQ[17]

DDR1_DQ[18]

DDR1_DQ[19]

DDR1_DQ[20]

DDR1_DQ[21]

DDR1_DQ[22]

DDR1_DQ[23]

DDR1_DQ[24]

DDR1_DQ[25]

DDR1_DQ[26]

DDR1_DQ[27]

DDR1_DQ[28]

DDR1_DQ[29]

DDR1_DQ[30]

DDR1_DQ[31]

DDR1_DQ[48]

DDR1_DQ[49]

DDR1_DQ[50]

DDR1_DQ[51]

DDR1_DQ[52]

DDR1_DQ[53]

DDR1_DQ[54]

DDR1_DQ[55]

DDR1_DQ[56]

DDR1_DQ[57]

DDR1_DQ[58]

DDR1_DQ[59]

DDR1_DQ[60]

DDR1_DQ[61]

DDR1_DQ[62]

DDR1_DQ[63]

DDR1_DQ[0]

DDR1_DQ[1]

DDR1_DQ[2]

DDR1_DQ[3]

DDR1_DQ[4]

DDR1_DQ[5]

DDR1_DQ[6]

DDR1_DQ[7]

DDR1_DQ[8]

DDR1_DQ[9]

DDR1_DQ[10]

DDR1_DQ[11]

DDR1_DQ[12]

DDR1_DQ[13]

DDR1_DQ[14]

DDR1_DQ[15]

LOGIC

Block 1

Non-Interleave

Block 3

Interleave

Non-Interleave

AH66

AH65

AG69

AG70

AR66

AR65

AR61

AR60

AT38

AR38

AT32

AR32

AR25

AR27

AR22

AR21

Block 1

Block 3

Block 5

Block 7

LOGIC

AY48

AP50

BA48

BB48

AP48

AP52

AN50

AN48

AN53

AN52

DDR1_CAA[0]

DDR1_CAA[1]

DDR1_CAA[2]

DDR1_CAA[3]

DDR1_CAA[4]

DDR1_CAA[5]

DDR1_CAA[6]

DDR1_CAA[7]

DDR1_CAA[8]

DDR1_CAA[9]

LOGIC

DDR1_MA[5]

DDR1_MA[9]

DDR1_MA[6]

DDR1_MA[8]

DDR1_MA[7]

DDR1_BA[2]

DDR1_MA[12]

DDR1_MA[11]

DDR1_MA[15]

DDR1_MA[14]

DDR1_MA[5]

DDR1_MA[9]

DDR1_MA[6]

DDR1_MA[8]

DDR1_MA[7]

DDR1_BG[0]

DDR1_MA[12]

DDR1_MA[11]

DDR1_ACT#

DDR1_BG[1]

BA43

AY 43

AY 44

AW44

BB44

AY 4 7

BA44

AW46

AY 4 6

BA46

BB46

BA47

DDR3L LPDDR3 DDR4

DDR1_MA[13]

DDR1_CAS#

DDR1_WE#

DDR1_RAS#

DDR1_BA[0]

DDR1_MA[2]

DDR1_BA[1]

DDR1_MA[10]

DDR1_MA[1]

DDR1_MA[0]

DDR1_MA[3]

DDR1_MA[4]

DDR1_CAB[0]

DDR1_CAB[1]

DDR1_CAB[2]

DDR1_CAB[3]

DDR1_CAB[4]

DDR1_CAB[5]

DDR1_CAB[6]

DDR1_CAB[7]

DDR1_CAB[8]

DDR1_CAB[9]

Not Used

DDR1_MA[13]

DDR1_MA[15]

DDR1_MA[14]

DDR1_MA[16]

DDR1_BA[0]

DDR1_MA[2]

DDR1_BA[1]

DDR1_MA[10]

DDR1_MA[1]

DDR1_MA[0]

DDR1_MA[3]

DDR1_MA[4]

DDR1_DQ[32]

DDR1_DQ[33]

DDR1_DQ[34]

DDR1_DQ[35]

DDR1_DQ[36]

DDR1_DQ[37]

DDR1_DQ[38]

DDR1_DQ[39]

DDR1_DQ[40]

DDR1_DQ[41]

DDR1_DQ[42]

DDR1_DQ[43]

DDR1_DQ[44]

DDR1_DQ[45]

DDR1_DQ[46]

DDR1_DQ[47]

DDR0_DQ[48]

DDR0_DQ[49]

DDR0_DQ[50]

DDR0_DQ[51]

DDR0_DQ[52]

DDR0_DQ[53]

DDR0_DQ[54]

DDR0_DQ[55]

DDR0_DQ[56]

DDR0_DQ[57]

DDR0_DQ[58]

DDR0_DQ[59]

DDR0_DQ[60]

DDR0_DQ[61]

DDR0_DQ[62]

DDR0_DQ[63]

DDR1_DQ[48]

DDR1_DQ[49]

DDR1_DQ[50]

DDR1_DQ[51]

DDR1_DQ[52]

DDR1_DQ[53]

DDR1_DQ[54]

DDR1_DQ[55]

DDR1_DQ[56]

DDR1_DQ[57]

DDR1_DQ[58]

DDR1_DQ[59]

DDR1_DQ[60]

DDR1_DQ[61]

DDR1_DQ[62]

DDR1_DQ[63]

DDR1_DQSN[0]

DDR1_DQSP[0]

DDR1_DQSN[1]

DDR1_DQSP[1]

DDR0_DQSN[6]

DDR0_DQSP[6]

DDR0_DQSN[7]

DDR0_DQSP[7]

DDR0_DQSN[2]

DDR0_DQSP[2]

DDR0_DQSN[3]

DDR0_DQSP[3]

DDR1_DQSN[2]

DDR1_DQSP[2]

DDR1_DQSN[3]

DDR1_DQSP[3]

DDR1_DQSN[6]

DDR1_DQSP[6]

DDR1_DQSN[7]

DDR1_DQSP[7]

DDR1_DQSN[4]

DDR1_DQSP[4]

DDR1_DQSN[5]

DDR1_DQSP[5]

DDR1_DQSN[6]

DDR1_DQSP[6]

DDR1_DQSN[7]

DDR1_DQSP[7]

DDR1_DQ[16]

DDR1_DQ[17]

DDR1_DQ[18]

DDR1_DQ[19]

DDR1_DQ[20]

DDR1_DQ[21]

DDR1_DQ[22]

DDR1_DQ[23]

DDR1_DQ[24]

DDR1_DQ[25]

DDR1_DQ[26]

DDR1_DQ[27]

DDR1_DQ[28]

DDR1_DQ[29]

DDR1_DQ[30]

DDR1_DQ[31]

DDR0_DQ[16]

DDR0_DQ[17]

DDR0_DQ[18]

DDR0_DQ[19]

DDR0_DQ[20]

DDR0_DQ[21]

DDR0_DQ[22]

DDR0_DQ[23]

DDR0_DQ[24]

DDR0_DQ[25]

DDR0_DQ[26]

DDR0_DQ[27]

DDR0_DQ[28]

DDR0_DQ[29]

DDR0_DQ[30]

DDR0_DQ[31]

DDR1_DQSN[2]

DDR1_DQSP[2]

DDR1_DQSN[3]

DDR1_DQSP[3]

TABL E

M_B_DQ5

-M_B_CS0

-M_B_DDRCLK0_1066M

M_B_CKE0

M_B_DDRCLK0_1066M

-M_B_CS1

M_B_CKE1

-M_B_DDRCLK1_1066M

M_B_DDRCLK1_1066M

M_B_DQ7

M_B_DQ6

M_B_DQ0

M_B_DQ1

M_B_DQ2

M_B_DQ3

M_B_DQ10

M_B_DQ14

M_B_DQ13

M_B_DQ9

M_B_DQ11

M_B_DQ15

M_B_DQ8

M_B_DQ12

M_B_DQ16

M_B_DQ23

M_B_DQ17

M_B_DQ21

M_B_DQ20

M_B_DQ18

M_B_DQ19

M_B_DQ22

M_B_DQ28

M_B_DQ24

M_B_DQ31

M_B_DQ27

M_B_DQ29

M_B_DQ25

M_B_DQ30

M_B_DQ26

M_B_DQ36

M_B_DQ33

M_B_DQ34

M_B_DQ38

M_B_DQ32

M_B_DQ37

M_B_DQ39

M_B_DQ35

M_B_DQ40

M_B_DQ44

M_B_DQ42

M_B_DQ46

M_B_DQ41

M_B_DQ45

M_B_DQ43

M_B_DQ47

M_B_DQ54

M_B_DQ52

M_B_DQ55

M_B_DQ50

M_B_DQ49

M_B_DQ53

M_B_DQ48

M_B_DQ51

M_B_DQ56

M_B_DQ61

M_B_DQ57

M_B_DQ59

M_B_DQ60

M_B_DQ62

M_B_DQ63

M_B_DQ58

M_B_A0

M_B_A1

M_B_A2

M_B_A3

M_B_A4

M_B_A5

M_B_A6

M_B_A7

M_B_A8

M_B_A9

M_B_A10

M_B_A11

M_B_A12

M_B_A13

M_B_BG1

-M_B_ACT

M_B_BS1

M_B_BG0

M_B_BS0

M_B_A15

M_B_A16

M_B_A14

-M_B_DQS0

-M_B_DQS1

-M_B_DQS2

-M_B_DQS3

-M_B_DQS4

-M_B_DQS5

-M_B_DQS6

-M_B_DQS7

M_B_DQS0

M_B_DQS1

M_B_DQS2

M_B_DQS3

M_B_DQS4

M_B_DQS5

M_B_DQS6

M_B_DQS7

-DRAMRST

M_B_DQ4

-M_B_ALERT

M_B_ODT0

M_B_ODT1

M_B_PARITY

-M_B_DQS[7:0] 24

M_B_DQS[7:0] 24

-DRAMRST 22,24

-M_B_DDRCLK0_1066M 24

-M_B_DDRCLK1_1066M 24

M_B_DDRCLK0_1066M 24

M_B_DDRCLK1_1066M 24

M_B_CKE0 24

M_B_CKE1 24

-M_B_CS0 24

-M_B_CS1 24

M_B_BG0 24

M_B_BS0 24

M_B_BS1 24

M_B_A[16:0] 24

M_B_DQ[63:0]24

M_B_ODT1 24

M_B_ODT0 24

-M_B_ACT 24

M_B_BG1 24

M_B_PARITY 24

-M_B_ALERT 24

VCC1R2A

Size

Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Deciphered Date

Title

Thorpe-2 UMA

0.01

CPU(3/16) : DDR CHANNEL-B

Custom

5 103

Wednesday, October 26, 2016

2012/07/01

2014/07/01

Size

Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Deciphered Date

Title

Thorpe-2 UMA

0.01

CPU(3/16) : DDR CHANNEL-B

Custom

5 103

Wednesday, October 26, 2016

2012/07/01

2014/07/01

Size

Document Number Rev

Date: Sheet of

Security Classification

LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Issued Date

Deciphered Date

Title

Thorpe-2 UMA

0.01

CPU(3/16) : DDR CHANNEL-B

Custom

5 103

Wednesday, October 26, 2016

2012/07/01

2014/07/01

SKL_ULT

DDR CH - B

3 OF 20

U58C

Kaby lake-U_BGA1356

DDR_RCOMP[0]

AR18

DDR_RCOMP[1]

AT18

DDR_RCOMP[2]

AU18

DDR1_ALERT#

AN43

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

BB44

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

BA44

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]

AP52

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

AY43

DDR1_CKE[0]

AN56

DDR1_CKE[1]

AP55

DDR1_CKE[2]

AN55

DDR1_CKE[3]

AP53

DDR1_CKN[0]

AN45

DDR1_CKN[1]

AN46

DDR1_CKP[0]

AP45

DDR1_CKP[1]

AP46

DDR1_CS#[0]

BB42

DDR1_CS#[1]

AY42

DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

BA46

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]

AY46

DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

AW46

DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

AN48

DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]

AN50

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

BA43

DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

AN52

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#

AN53

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

AY47

DDR1_MA[3]

BB46

DDR1_MA[4]

BA47

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]

AY48

DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]

BA48

DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

AP48

DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]

BB48

DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]

AP50

DDR1_ODT[0]

BA42

DDR1_ODT[1]

AW42

DDR1_PAR

AP43

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

AW44

DDR1_W E#/DDR1_CAB[2]/DDR1_MA[14]

AY44

DDR1_DQ[0]/DDR0_DQ[16]

AF65

DDR1_DQ[1]/DDR0_DQ[17]

AF64

DDR1_DQ[2]/DDR0_DQ[18]

AK65

DDR1_DQ[3]/DDR0_DQ[19]

AK64

DDR1_DQ[4]/DDR0_DQ[20]

AF66

DDR1_DQ[5]/DDR0_DQ[21]

AF67

DDR1_DQ[6]/DDR0_DQ[22]

AK67

DDR1_DQ[7]/DDR0_DQ[23]

AK66

DDR1_DQ[8]/DDR0_DQ[24]

AF70

DDR1_DQ[9]/DDR0_DQ[25]

AF68

DDR1_DQ[10]/DDR0_DQ[26]

AH71

DDR1_DQ[11]/DDR0_DQ[27]

AH68

DDR1_DQ[12]/DDR0_DQ[28]

AF71

DDR1_DQ[13]/DDR0_DQ[29]

AF69

DDR1_DQ[14]/DDR0_DQ[30]

AH70

DDR1_DQ[15]/DDR0_DQ[31]

AH69

DDR1_DQ[16]/DDR0_DQ[48]

AT66

DDR1_DQ[17]/DDR0_DQ[49]

AU66

DDR1_DQ[18]/DDR0_DQ[50]

AP65

DDR1_DQ[19]/DDR0_DQ[51]

AN65

DDR1_DQ[20]/DDR0_DQ[52]

AN66

DDR1_DQ[21]/DDR0_DQ[53]

AP66

DDR1_DQ[22]/DDR0_DQ[54]

AT65

DDR1_DQ[23]/DDR0_DQ[55]

AU65

DDR1_DQ[24]/DDR0_DQ[56]

AT61

DDR1_DQ[25]/DDR0_DQ[57]

AU61

DDR1_DQ[26]/DDR0_DQ[58]

AP60

DDR1_DQ[27]/DDR0_DQ[59]

AN60

DDR1_DQ[28]/DDR0_DQ[60]

AN61

DDR1_DQ[29]/DDR0_DQ[61]

AP61

DDR1_DQ[30]/DDR0_DQ[62]

AT60

DDR1_DQ[31]/DDR0_DQ[63]

AU60

DDR1_DQ[32]/DDR1_DQ[16]

AU40

DDR1_DQ[33]/DDR1_DQ[17]

AT40

DDR1_DQ[34]/DDR1_DQ[18]

AT37

DDR1_DQ[35]/DDR1_DQ[19]

AU37

DDR1_DQ[36]/DDR1_DQ[20]

AR40

DDR1_DQ[37]/DDR1_DQ[21]

AP40

DDR1_DQ[38]/DDR1_DQ[22]

AP37

DDR1_DQ[39]/DDR1_DQ[23]

AR37

DDR1_DQ[40]/DDR1_DQ[24]

AT33

DDR1_DQ[41]/DDR1_DQ[25]

AU33

DDR1_DQ[42]/DDR1_DQ[26]

AU30

DDR1_DQ[43]/DDR1_DQ[27]

AT30

DDR1_DQ[44]/DDR1_DQ[28]

AR33

DDR1_DQ[45]/DDR1_DQ[29]

AP33

DDR1_DQ[46]/DDR1_DQ[30]

AR30

DDR1_DQ[47]/DDR1_DQ[31]

AP30

DDR1_DQ[48]

AU27

DDR1_DQ[49]

AT27

DDR1_DQ[50]

AT25

DDR1_DQ[51]

AU25

DDR1_DQ[52]

AP27

DDR1_DQ[53]

AN27

DDR1_DQ[54]

AN25

DDR1_DQ[55]

AP25

DDR1_DQ[56]

AT22

DDR1_DQ[57]

AU22

DDR1_DQ[58]

AU21

DDR1_DQ[59]

AT21

DDR1_DQ[60]

AN22

DDR1_DQ[61]

AP22

DDR1_DQ[62]

AP21

DDR1_DQ[63]

AN21

DDR1_DQSN[0]/DDR0_DQSN[2]

AH66

DDR1_DQSN[1]/DDR0_DQSN[3]

AG69

DDR1_DQSN[2]/DDR0_DQSN[6]

AR66

DDR1_DQSN[3]/DDR0_DQSN[7]

AR61

DDR1_DQSN[4]/DDR1_DQSN[2]

AT38

DDR1_DQSN[5]/DDR1_DQSN[3]

AT32

DDR1_DQSN[6]

AR25

DDR1_DQSN[7]

AR22

DDR1_DQSP[0]/DDR0_DQSP[2]

AH65

DDR1_DQSP[1]/DDR0_DQSP[3]

AG70

DDR1_DQSP[2]/DDR0_DQSP[6]

AR65

DDR1_DQSP[3]/DDR0_DQSP[7]

AR60

DDR1_DQSP[4]/DDR1_DQSP[2]

AR38

DDR1_DQSP[5]/DDR1_DQSP[3]

AR32

DDR1_DQSP[6]

AR27

DDR1_DQSP[7]

AR21

DRAM_RESET#

AT13

R84 80.6_0201_1%

1 2

R576 100_0201_1%

1 2

R1726

470_0201_5%

1 2

R7 121_0201_1%

1 2

剩余102页未读，继续阅读

daiwee

2023-07-27

文档不错，就是少了点位图！

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资源: 29

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