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MPC5606S芯片用户手册
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该文件是Freescale公司MPC5606S用户手册,对于开发3.5寸彩屏仪表有使用帮助。
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MPC5606S Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 1
MPC5606S Microcontroller
Reference Manual
Devices Supported:
MPC5602S
MPC5604S
MPC5606S
MPC5606SRM
Rev. 5
4 May 2010
单片机引脚定义在P85页
MPC5606S Microcontroller Reference Manual, Rev. 5
2 Freescale Semiconductor
MPC5606S Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 3
Chapter 1
Overview
1.1 Introduction .....................................................................................................................................43
1.2 MPC5606S family comparison .......................................................................................................45
1.3 Block diagram .................................................................................................................................48
1.4 Chip-level features ..........................................................................................................................48
1.5 Feature details .................................................................................................................................51
1.5.1 Low-power operation .....................................................................................................51
1.5.2 e200z0h core processor ..................................................................................................54
1.5.3 Crossbar switch (XBAR) ................................................................................................56
1.5.4 Enhanced Direct Memory Access (eDMA) ...................................................................56
1.5.5 Inter-IC communications module (I2C) .........................................................................57
1.5.6 Interrupt Controller (INTC) ............................................................................................57
1.5.7 QuadSPI serial flash controller .......................................................................................58
1.5.8 System Integration Unit (SIU) ........................................................................................58
1.5.9 Flash memory .................................................................................................................59
1.5.10 SRAM .............................................................................................................................59
1.5.11 On-chip graphics SRAM ................................................................................................59
1.5.12 Memory Protection Unit (MPU) ....................................................................................60
1.5.13 Boot Assist Module (BAM) ...........................................................................................60
1.5.14 Enhanced Modular Input/Output System (eMIOS) ........................................................60
1.5.15 Analog-to-Digital Converter (ADC) ..............................................................................62
1.5.16 Deserial Serial Peripheral Interface (DSPI) ...................................................................63
1.5.17 FlexCAN .........................................................................................................................63
1.5.18 Serial communication interface module (LINFlex) .......................................................64
1.5.19 System clocks and clock generation modules ................................................................65
1.5.20 Periodic Interrupt Timer module (PIT) ..........................................................................66
1.5.21 Real Time Counter (RTC) ..............................................................................................66
1.5.22 System Timer Module (STM) ........................................................................................66
1.5.23 Software Watchdog Timer (SWT) ..................................................................................67
1.5.24 Display Control Unit (DCU) ..........................................................................................67
1.5.25 Parallel Data Interface (PDI) ..........................................................................................68
1.5.26 Liquid Crystal Display (LCD) driver .............................................................................68
1.5.27 Stepper Motor Controller (SMC) ...................................................................................69
1.5.28 Stepper Stall Detect (SSD) .............................................................................................70
1.5.29 Sound Generation Logic (SGL) ......................................................................................70
1.5.30 IEEE 1149.1 JTAG Controller (JTAGC) ........................................................................70
1.5.31 Nexus Development Interface (NDI) .............................................................................70
1.6 Developer environment ...................................................................................................................71
1.7 How to use the MPC5606S documents ...........................................................................................71
1.7.1 The MPC5606S document set ........................................................................................71
1.7.2 Reference manual content ..............................................................................................72
1.8 Using the MPC5606S ......................................................................................................................73
1.8.1 Hardware design .............................................................................................................74
1.8.2 Input/output pins .............................................................................................................74
MPC5606S Microcontroller Reference Manual, Rev. 5
4 Freescale Semiconductor
1.8.3 Software design ..............................................................................................................75
1.8.4 Other features .................................................................................................................76
Chapter 2
Memory Map
Chapter 3
Signal Description
3.1 Introduction .....................................................................................................................................83
3.2 Package pinouts ...............................................................................................................................84
3.3 Pad configuration during reset phases .............................................................................................87
3.4 Voltage supply pins .........................................................................................................................87
3.5 Pad types .........................................................................................................................................88
3.6 System pins .....................................................................................................................................89
3.7 Debug pins .......................................................................................................................................89
3.8 Functional ports ...............................................................................................................................91
3.9 Signal details .................................................................................................................................109
Chapter 4
Safety
4.1 Register protection ........................................................................................................................113
4.1.1 Introduction ..................................................................................................................113
4.1.1.1 Overview ........................................................................................................113
4.1.1.2 Features ..........................................................................................................113
4.1.1.3 Modes of Operation .......................................................................................114
4.1.2 External Signal Description ..........................................................................................114
4.1.3 Memory Map and Register Description .......................................................................114
4.1.3.1 Memory map ..................................................................................................115
4.1.3.2 Register Description .......................................................................................116
4.1.4 Functional Description .................................................................................................118
4.1.4.1 General ...........................................................................................................118
4.1.4.2 Change Lock Settings ....................................................................................119
4.1.4.3 Access Errors .................................................................................................121
4.1.5 Reset .............................................................................................................................122
4.2 Software Watchdog Timer (SWT) .................................................................................................122
4.2.1 Overview ......................................................................................................................122
4.2.2 Features .........................................................................................................................122
4.2.3 Modes of operation .......................................................................................................123
4.2.4 External signal description ...........................................................................................124
4.2.5 Memory map and register description ..........................................................................124
4.2.5.1 Memory map ..................................................................................................124
4.2.5.2 SWT Control Register (SWT_CR) ................................................................125
4.2.5.3 SWT Interrupt Register (SWT_IR) ................................................................126
4.2.5.4 SWT Time-Out Register (SWT_TO) .............................................................127
4.2.6 Functional Description .................................................................................................129
MPC5606S Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 5
Chapter 5
Analog-to-Digital Converter (ADC)
5.1 Overview .......................................................................................................................................131
5.1.1 Device-specific features ...............................................................................................131
5.1.2 Device-specific implementation ...................................................................................132
5.2 Introduction ...................................................................................................................................132
5.3 Functional description ...................................................................................................................133
5.3.1 Analog channel conversion ..........................................................................................133
5.3.1.1 Normal conversion .........................................................................................133
5.3.1.2 Start of normal conversion .............................................................................133
5.3.1.3 Normal conversion operating modes .............................................................134
5.3.1.4 Injected channel conversion ...........................................................................135
5.3.1.5 Abort conversion ............................................................................................136
5.3.2 Analog clock generator and conversion timings ..........................................................137
5.3.3 ADC sampling and conversion timing .........................................................................137
5.3.4 Programmable analog watchdog ..................................................................................139
5.3.4.1 Introduction ....................................................................................................139
5.3.5 DMA functionality .......................................................................................................140
5.3.6 Interrupts .......................................................................................................................140
5.3.7 External decode signals delay ......................................................................................141
5.3.8 Power-down mode ........................................................................................................141
5.3.9 Auto-clock-off mode ....................................................................................................141
5.4 Register descriptions .....................................................................................................................141
5.4.1 Introduction ..................................................................................................................141
5.4.2 Control logic registers ..................................................................................................145
5.4.2.1 Main Configuration Register (MCR) .............................................................145
5.4.2.2 Main Status Register (MSR) ..........................................................................148
5.4.3 Interrupt registers ..........................................................................................................149
5.4.3.1 Interrupt Status Register (ISR) .......................................................................149
5.4.3.2 Channel Pending Registers (CEOCFR[1..2]) ................................................150
5.4.3.3 Interrupt Mask Register (IMR) ......................................................................151
5.4.3.4 Channel Interrupt Mask Register (CIMR[1..2]) .............................................153
5.4.3.5 Watchdog Threshold Interrupt Status Register (WTISR) ..............................154
5.4.3.6 Watchdog Threshold Interrupt Mask Register (WTIMR) ..............................154
5.4.4 DMA registers ..............................................................................................................156
5.4.4.1 DMA Enable Register (DMAE) ....................................................................156
5.4.4.2 DMA Channel Select Register (DMAR[1..2]) ...............................................157
5.4.5 Threshold registers .......................................................................................................158
5.4.5.1 Introduction ....................................................................................................158
5.4.5.2 Threshold Control Register (TRCx, x = [0..3]) ..............................................158
5.4.5.3 Threshold Register (THRHLR[0:3]) ..............................................................159
5.4.6 Conversion timing registers CTR[1..2] ........................................................................160
5.4.7 Mask registers ...............................................................................................................161
5.4.7.1 Introduction ....................................................................................................161
5.4.7.2 Normal Conversion Mask Registers (NCMR[1..2]) ......................................161
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