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Architecture Guide
VideoCore® IV 3D
VideoCoreIV-AG100-R
5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203 September 16, 2013
VideoCore® IV 3D
Architecture Reference Guide
Broadcom®, the pulse logo, Connecting everything®, and the Connecting everything logo are among the
trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/
or the EU. Any other trademarks or trade names mentioned are the property of their respective owners.
Broadcom Corporation
5300 California Avenue
Irvine, CA 92617
© 2013 by Broadcom Corporation
All rights reserved
Printed in the U.S.A.
Revision History
Revision Date Change Description
VideoCoreIV-AG100-R 09/16/13 Initial release
Table of Contents VideoCore® IV 3D Architecture Guide
BROADCOM VideoCore® IV 3D Architecture Reference Guide
September 16, 2013 • VideoCoreIV-AG100-R Page 3
®
Table of Contents
About This Document...................................................................................................................................11
Purpose and Audience ...........................................................................................................................11
Acronyms and Abbreviations.................................................................................................................11
Document Conventions .........................................................................................................................11
Section 1: Introduction.................................................................................................... 12
Section 2: Architecture Overview .................................................................................... 13
Section 3: Quad Processor............................................................................................... 16
Quad Processor Architecture .......................................................................................................................17
Core Pipeline Operation.........................................................................................................................17
Processor Registers.........................................................................................................................17
ALUs ................................................................................................................................................18
Signaling Bits...................................................................................................................................19
Load Immediate..............................................................................................................................19
Small Immediates ...........................................................................................................................19
Branches .........................................................................................................................................20
Horizontal Vector Rotation.............................................................................................................20
Pack and Unpack.............................................................................................................................20
Thread Control .......................................................................................................................................20
Inter-Processor Synchronisation............................................................................................................22
Register-Mapped Input/Output.............................................................................................................22
Varyings ..........................................................................................................................................22
Uniforms .........................................................................................................................................22
Texture and Memory Units.............................................................................................................23
Special Functions Unit ....................................................................................................................23
Vertex Pipeline Memory.................................................................................................................24
Tile Buffer .......................................................................................................................................24
Inter-Processor Mutex....................................................................................................................24
Host Interrupt .................................................................................................................................24
Processor Stalls ......................................................................................................................................25
QPU Instruction Encoding ............................................................................................................................26
ALU Instructions.....................................................................................................................................26
Condition Codes..............................................................................................................................28
ALU Input Muxes ............................................................................................................................28
Table of Contents VideoCore® IV 3D Architecture Guide
BROADCOM VideoCore® IV 3D Architecture Reference Guide
September 16, 2013 • VideoCoreIV-AG100-R Page 4
®
Signaling Bits...................................................................................................................................29
Small Immediate.............................................................................................................................29
Pack/Unpack Bits ............................................................................................................................30
Load Immediate Instructions .................................................................................................................33
Semaphore Instruction ..........................................................................................................................33
Branch Instruction .................................................................................................................................34
QPU Instruction Set......................................................................................................................................35
Op Add ...................................................................................................................................................35
Op Mul ...................................................................................................................................................36
Summary of Instruction Restrictions ...........................................................................................................37
QPU Register Address Map ..........................................................................................................................37
Section 4: Texture and Memory Lookup Unit................................................................... 39
QPU Interface ...............................................................................................................................................39
Texture Data Storage ...................................................................................................................................40
Texture and Memory Lookup Unit Setup ....................................................................................................40
Texture Data Types ................................................................................................................................42
Texture Filter Types ...............................................................................................................................43
Texture Modes.......................................................................................................................................44
Normal 2D Texture Mode ...............................................................................................................44
Cube Map Mode .............................................................................................................................44
Interface Registers .................................................................................................................................44
Section 5: Tile Buffer ....................................................................................................... 46
QPU Interface ...............................................................................................................................................47
Scoreboard.............................................................................................................................................47
Color Read and Write.............................................................................................................................47
Z and Stencil...........................................................................................................................................47
Coverage Read .......................................................................................................................................48
Tile Buffer Access Restrictions ...............................................................................................................48
QPU Registers for Tile Buffer Access............................................................................................................49
Section 6: FEP-to-QPU Interface ...................................................................................... 51
Initial Data ....................................................................................................................................................51
Varyings Interpolation..................................................................................................................................51
Section 7: VPM and VCD.................................................................................................. 53
QPU Reading and Writing of VPM ...............................................................................................................53
QPU Control of VCD and VDW .....................................................................................................................56
Table of Contents VideoCore® IV 3D Architecture Guide
BROADCOM VideoCore® IV 3D Architecture Reference Guide
September 16, 2013 • VideoCoreIV-AG100-R Page 5
®
QPU Registers for VPM and VCD Functions.................................................................................................57
VPM Vertex Data Formats............................................................................................................................60
Vertex Attribute Format in VPM from VCD ...........................................................................................60
Shaded Vertex Format in VPM for PSE ..................................................................................................60
Shaded Coordinates Format in VPM for PTB .........................................................................................61
Section 8: System Control................................................................................................ 62
System Operation.........................................................................................................................................62
System Pipelines and Modes .......................................................................................................................63
Section 9: Control Lists .................................................................................................... 65
Control Record IDs and Data Summary .......................................................................................................65
Primitive List Formats...................................................................................................................................72
VG Coordinate Array Primitives (ID=41) ................................................................................................72
VG Inline Primitives (ID=42) ...................................................................................................................72
Compressed Primitive List (ID=48).........................................................................................................72
Clipped Primitive (with Compressed Primitive List) (ID=49)..................................................................78
Shader State Record Formats.......................................................................................................................78
Shaded Vertex Format in Memory...............................................................................................................81
Section 10: V3D Registers................................................................................................ 82
V3D Register Address Map...........................................................................................................................82
V3D Register Definitions ..............................................................................................................................85
Control List Executor Registers (Per Thread) .........................................................................................85
V3D Pipeline Registers ...........................................................................................................................87
QPU Scheduler Registers .......................................................................................................................89
VPM Registers........................................................................................................................................92
Cache Control Registers .........................................................................................................................93
QPU Interrupt Control ...........................................................................................................................94
Pipeline Interrupt Control......................................................................................................................95
V3D Miscellaneous Registers .................................................................................................................96
V3D Identity Registers ...........................................................................................................................96
Performance Counters...........................................................................................................................97
Error and Diagnostic Registers.............................................................................................................100
Section 11: Texture Memory Formats............................................................................ 105
Micro-tiles...................................................................................................................................................105
Texture Format (T-format) .........................................................................................................................105
Linear-tile Format (LT-Format)...................................................................................................................107
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