没有合适的资源?快使用搜索试试~ 我知道了~
首页vivado -sysgen tutorial
资源详情
资源评论
资源推荐
Vivado Design Suite Tutorial
Model-Based DSP Design Using
System Generator
UG948 (v2017.3) October 4, 2017
Model-Based DSP Design Using System Generator 2
UG948 (v2017.3) October 4, 2017 www.xilinx.com
Revision History
The following table shows the revision history for this document.
Date Version Changes
10/04/2017 2017.3 Validated for Vivado® Design Suite 2017.3. Changes include:
• Updated design files so Tutorial would produce correct results in
Vivado Design Suite 2017.3.
• Updated Figures to show results for 2017.3 release.
06/07/2017 2017.2 Released with Vivado Design Suite 2017.2 without changes from the
previous release.
04/28/2017 2017.1 Validated for Vivado® Design Suite 2017.1. Changes include:
• Reorganized and combined Labs to improve the flow of the
Tutorial.
• Updated text and screen displays in accordance with the
renumbered Labs.
• Added Lab 3: Timing and Resource Analysis, describing how the
timing analyzer can be used to detect timing violations and how
the resource analyzer can be used to predict resource usage in
the programmed Xilinx device.
• Updated content based on the new Vivado IDE look and feel.
Updated all Figures showing dialog boxes, windows, and screen
areas in the Vivado IDE.
Send Feedback
Model-Based DSP Design Using System Generator 3
UG948 (v2017.3) October 4, 2017 www.xilinx.com
Table of Contents
Revision History ..................................................................................................................................................2
System Generator for DSP Overview ......................................................................................................................5
Introduction ........................................................................................................................................................5
Software Requirements ......................................................................................................................................7
Configuring MATLAB to the Vivado Design Suite ...............................................................................................7
Locating and Preparing the Tutorial Design Files ...............................................................................................8
Lab 1: Introduction to System Generator ...............................................................................................................9
Introduction ........................................................................................................................................................9
Step 1: Creating a Design in an FPGA .............................................................................................................. 10
Step 2: Creating an Optimized Design in an FPGA .......................................................................................... 24
Step 3: Creating a Design Using Discrete Resources ....................................................................................... 28
Step 4: Working with Data Types .................................................................................................................... 38
Summary .......................................................................................................................................................... 50
Lab 2: Importing Code into System Generator .................................................................................................... 51
Step 1: Modeling Control with M-Code ........................................................................................................... 51
Step 2: Modeling Blocks with HDL ................................................................................................................... 55
Step 3 : Modeling Blocks with C/C++ code ...................................................................................................... 61
Summary .......................................................................................................................................................... 69
Lab 3: Timing and Resource Analysis ................................................................................................................... 70
Introduction ..................................................................................................................................................... 70
Step 1: Timing Analysis in System Generator .................................................................................................. 70
Step 2: Resource Analysis in System Generator .............................................................................................. 77
Summary .......................................................................................................................................................... 81
Lab 4: Working with Multi-Rate Systems ............................................................................................................ 82
Introduction ..................................................................................................................................................... 82
Step 1: Creating Clock Domain Hierarchies ..................................................................................................... 82
Step 2: Creating Asynchronous Channels ........................................................................................................ 86
Step 3: Specifying Clock Domains .................................................................................................................... 91
Send Feedback
Table of Contents
Model-Based DSP Design Using System Generator 4
UG948 (v2017.3) October 4, 2017 www.xilinx.com
Summary .......................................................................................................................................................... 96
Lab 5: Using AXI Interfaces and IP Integrator ...................................................................................................... 97
Introduction ..................................................................................................................................................... 97
Step 1: Review the AXI Interfaces.................................................................................................................... 98
Step 2: Create a Vivado Project using System Generator IP ........................................................................... 99
Step 3: Create a Design in IP Integrator (IPI) ................................................................................................. 102
Step 4: Implement the Design ....................................................................................................................... 109
Summary ........................................................................................................................................................ 110
Lab 6: Using a System Generator Design with a Zynq-7000 AP SoC ................................................................. 111
Introduction ................................................................................................................................................... 111
Step 1: Review the AXI4-Lite Interface Drivers.............................................................................................. 112
Step 2: Developing Software and Running it on the ZYNQ-7000 System ..................................................... 115
Summary ........................................................................................................................................................ 120
Legal Notices ...................................................................................................................................................... 121
Please Read: Important Legal Notices ........................................................................................................... 121
Send Feedback
Model-Based DSP Design Using System Generator 5
UG948 (v2017.3) October 4, 2017 www.xilinx.com
System Generator for DSP Overview
Introduction
System Generator for DSP is a design tool in the Vivado
®
Design Suite that enables you to use the
MathWorks
®
model-based Simulink® design environment for FPGA design. Previous experience with
Xilinx
®
FPGA devices or RTL design methodologies is not required when using System Generator.
Designs are captured in the Simulink™ modeling environment using a Xilinx-specific block set.
Downstream FPGA steps including RTL synthesis and implementation (where the gate level design is
placed and routed in the FPGA) are automatically performed to produce an FPGA programming
bitstream.
Over 80 building blocks are included in the Xilinx-specific DSP block set for Simulink. These blocks
include common building blocks such as adders, multipliers and registers. Also included are complex
DSP building blocks such as forward-error-correction blocks, FFTs, filters, and memories. These complex
blocks leverage Xilinx LogiCORE™ IP to produce optimized results for the selected target device.
VIDEO:
The Vivado Design Suite Quick Take Video Tutorial: System Generator Multiple Clock
Domains describes how to use Multiple Clock Domains within System Generator, making it possible to
implement complex DSP systems.
VIDEO:
The Vivado Design Suite QuickTake Video Tutorial: Generating Vivado HLS block for use in
System Generator for DSP describes how to generate a Vivado HLS IP block for use in System Generator,
and ends with a summary of how the Vivado HLS block can be used in your System Generator design.
VIDEO:
The Vivado Design Suite Quick Take Video: Using Vivado HLS C/C++/System C block in
System Generator describes how to incorporate your Vivado HLS design as an IP block into System Generator
for DSP.
Send Feedback
剩余120页未读,继续阅读
yeyazi
- 粉丝: 25
- 资源: 24
上传资源 快速赚钱
- 我的内容管理 收起
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
会员权益专享
最新资源
- zigbee-cluster-library-specification
- JSBSim Reference Manual
- c++校园超市商品信息管理系统课程设计说明书(含源代码) (2).pdf
- 建筑供配电系统相关课件.pptx
- 企业管理规章制度及管理模式.doc
- vb打开摄像头.doc
- 云计算-可信计算中认证协议改进方案.pdf
- [详细完整版]单片机编程4.ppt
- c语言常用算法.pdf
- c++经典程序代码大全.pdf
- 单片机数字时钟资料.doc
- 11项目管理前沿1.0.pptx
- 基于ssm的“魅力”繁峙宣传网站的设计与实现论文.doc
- 智慧交通综合解决方案.pptx
- 建筑防潮设计-PowerPointPresentati.pptx
- SPC统计过程控制程序.pptx
资源上传下载、课程学习等过程中有任何疑问或建议,欢迎提出宝贵意见哦~我们会及时处理!
点击此处反馈
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功
评论0