Quartus II v15官方手册：FPGA设计与合成指南

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Figure 1-13: IP Parameter Editors

View IP port

and parameter

details

Apply preset parameters for

specific applications

Specify your IP variation

name and target device

Legacy parameter

editors

Adding IP Cores to IP Catalog

The IP Catalog automatically displays Altera IP cores found in the project directory, in the Altera

installation directory, and in the defined IP search path. The IP Catalog can include Altera-provided IP

components, third-party IP components, custom IP components that you provide, and previously

generated Qsys systems.

You can use the IP Search Path option (Tools > Options) to include custom and third-party IP

components in the IP Catalog. The IP Catalog displays all IP cores in the IP search path. The Quartus II

software searches the directories listed in the IP search path for the following IP core files:

• Component Description File (_hw.tcl)—Defines a single IP core.

• IP Index File (.ipx)—Each .ipx file indexes a collection of available IP cores, or a reference to other

directories to search. In general, .ipx files facilitate faster searches.

The Quartus II software searches some directories recursively and other directories only to a specific

depth. When the search is recursive, the search stops at any directory that contains an _hw.tcl or .ipx file.

In the following list of search locations, a recursive descent is annotated by **. A single * signifies any file.

Table 1-2: IP Search Locations

Location Description

PROJECT_DIR/*

Finds IP components and index files in the Quartus II project

directory.

PROJECT_DIR/ip/**/*

Finds IP components and index files in any subdirectory of the /ip

subdirectory of the Quartus II project directory.

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Adding IP Cores to IP Catalog

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Table 1-3: IP Core General Setting Locations

Setting Location Description

Tools > Options > IP

Settings

Assignments > Settings >

IP Settings (only enabled

with open project)

• Specify your IP generation HDL preference. The parameter editor

generates IP files in your preferred HDL by default.

• Increase Maximum Qsys memory usage size if you experience slow

processing for large systems, or if Qsys reports an Out of Memory error.

• Specify whether to Automatically add Quartus II IP files to all projects.

Disable this option to control addition of IP files manually. You may

want to experiment with IP before adding to a project.

• Use the IP Regeneration Policy setting to control when synthesis files

are regenerated for each IP variation. Typically you Always regenerate

synthesis files for IP cores after making changes to an IP variation.

Tools > Options > IP

Catalog Search Locations

Assignments > Settings >

IP Catalog Search

Locations

• Specify project and global IP search locations. The Quartus II software

searches for IP cores in the project directory, in the Altera installation

directory, and in the IP search path.

Assignments > Settings >

Simulation

• NativeLink Settings allow you to automatically compile testbenches for

supported simulators. You can also specify a script to compile the

testbench, and a script to set up the simulation.

Specifying IP Core Parameters and Options

You can quickly configure a custom IP variation in the parameter editor. Use the following steps to

specify IP core options and parameters in the parameter editor. Refer to Specifying IP Core Parameters

and Options (Legacy Parameter Editors) for configuration of IP cores using the legacy parameter editor.

1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.

The parameter editor appears.

2. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation

settings in a file named <your_ip>.qsys. Click OK.

3. Specify the parameters and options for your IP variation in the parameter editor, including one or

more of the following. Refer to your IP core user guide for information about specific IP core

parameters.

• Optionally select preset parameter values if provided for your IP core. Presets specify initial

parameter values for specific applications.

• Specify parameters defining the IP core functionality, port configurations, and device-specific

features.

• Specify options for processing the IP core files in other EDA tools.

4. Click Generate HDL, the Generation dialog box appears.

5. Specify output file generation options, and then click Generate. The IP variation files generate

according to your specifications.

QII5V1

2015.05.04

Specifying IP Core Parameters and Options

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Figure 1-16: IP Core Generated Files

<your_testbench>_tb.csv

<your_testbench>_tb.spd

<your_ip>.cmp - VHDL component declaration file

<your_ip>.ppf - XML I/O pin information file

<your_ip>.qip - Lists IP synthesis files

<your_ip>.sip - Contains assingments for IP simulation files

<your_ip>.v or .vhd

Top-level IP synthesis file

<your_ip>.v or .vhd

Top-level simulation file

<simulator_setup_scripts>

<your_ip>.qsys - System or IP integration file

<your_ip>_bb.v - Verilog HDL black box EDA synthesis file

<your_ip>_inst.v or .vhd - Sample instantiation template

<your_ip>_generation.rpt - IP generation report

<your_ip>.debuginfo - Contains post-generation information

<your_ip>.html - Connection and memory map data

<your_ip>.bsf - Block symbol schematic

<your_ip>.spd - Combines simulation scripts for multiple cores

<your_ip>_tb.qsys

Testbench system file

<your_ip>.sopcinfo - Software tool-chain integration file

<EDA tool setup

scripts>

<your_ip>

IP variation files

<testbench>_tb

testbench system

sim

Simulation files

synth

IP synthesis files

sim

simulation files

Simulator scripts

<testbench>_tb

<ip subcores> n

Subcore libraries

sim

Subcore

Simulation files

synth

Subcore

synthesis files

<your_ip> n

IP variation files

testbench files

Table 1-4: IP Core Generated Files

File Name Description

<my_ip>.qsys

The Qsys system or top-level IP variation file. <my_ip> is the name

that you give your IP variation.

<system>.sopcinfo Describes the connections and IP component parameterizations in

your Qsys system. You can parse its contents to get requirements

when you develop software drivers for IP components.

Downstream tools such as the Nios II tool chain use this file.

The .sopcinfo file and the system.h file generated for the Nios II tool

chain include address map information for each slave relative to each

master that accesses the slave. Different masters may have a different

address map to access a particular slave component.

QII5V1

2015.05.04

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