Xilinx FIFO IP核设计与配置指南

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Xilinx的FIFO Generator IP核是LogiCORE IP产品系列的一部分，专为设计高性能和可定制的数据流管理提供解决方案。这款v9.2版本的IP核文档详细介绍了FIFO (First-In-First-Out) 的工作原理、特性、应用以及在Vivado Design Suite中的使用方法。 **IP Facts - Overview** 该FIFO Generator支持两种接口类型：Native Interface FIFOs和AXI4 Interface FIFOs。Native Interface FIFOs直接与系统总线相连，适合简单的数据传输，而AXI4接口则提供了更高级别的一致性控制和性能优化，适用于AXI4兼容的硬件平台。功能概览部分列出了核心特性，包括但不限于深度可配置、读写操作控制、以及数据计数器等。 **Product Specification** 在性能方面，FIFO Generator考虑了吞吐量、资源利用率以及延迟。设计者可以预期在合理配置下，它能高效地处理数据流，同时保证系统的功耗和面积效率。章节中还详细描述了各个端口的功能，如数据输入/输出端口、读写控制信号、时钟和复位接口等。 **Designing with the Core** 设计指南涵盖了如何初始化FIFO、控制数据读写、处理时钟和复位信号，以及确定实际的FIFO深度和可能的延迟。此外，文档还提到了一些特殊设计注意事项，如如何正确重置FIFO、处理连续时钟、避免数据完整性问题（如setup and hold time violations）以及对写入数据计数和读取数据计数的管理。 **Vivado Design Suite Customization** 对于Vivado用户，文档重点讲解了如何通过GUI定制并生成两种类型的FIFO核：Native Core和AXI4 Core。GUI界面直观易用，允许用户配置参数，如深度、宽度和接口配置。输出生成部分指导用户如何将定制的IP核集成到Vivado设计流程中，确保与其他IP块的协同工作。 Xilinx FIFO Generator IP核文档为设计者提供了全面的设计指南，包括接口配置、性能参数、设计流程和定制选项，旨在帮助用户快速构建出满足特定应用需求的高效FIFO逻辑。通过遵循这份文档，开发人员可以充分利用FIFO的灵活性和功能，优化其在Xilinx FPGA或ASIC设计中的性能。

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PG057 July 25, 2012

Feature Summary

Common Clock: Block RAM, Distributed RAM, Shift Register

This implementation category allows the user to select block RAM, distributed RAM, or shift

supported for this configuration includes status flags (full, almost full, empty, and almost

empty) and programmable empty and full flags generated with user-defined thresholds.

In addition, optional handshaking and error flags are supported (write acknowledge,

overflow, valid, and underflow), and an optional data count provides the number of words

in the FIFO. In addition, for the block RAM and distributed RAM implementations, the user

has the option to select a synchronous or asynchronous reset for the core. For Zynq-7000,

7 series, Virtex-6 and Virtex-5 FPGA designs, the block RAM FIFO configuration also

supports ECC.

Common Clock: Zynq-7000, 7 Series, Virtex-6, Virtex-5 or Virtex-4 FPGA

Built-in FIFO

This implementation category allows the user to select the built-in FIFO available in the

Zynq-7000, 7 series, Virtex-6, Virtex-5 or Virtex-4 FPGA architecture and supports a

common clock for write and read data accesses. The feature set supported for this

configuration includes status flags (full and empty) and optional programmable full and

empty flags with user-defined thresholds.

In addition, optional handshaking and error flags are available (write acknowledge,

overflow, valid, and underflow). The Zynq-7000, 7 series, Virtex-6 and Virtex-5 FPGA built-in

FIFO configuration also supports the built-in ECC feature.

Table 1-3: FIFO Configurations

Clock Domain Memory Type

Non-symmetri

c Aspect

Ratios

First-word

Fall-Through

ECC

Support

Embedded

Support

Common Block RAM  

a. Embedded register support is only available for Zynq-7000, 7 series, Virtex-6, Virtex-5 and Virtex-4 FPGA block

RAM-based FIFOs, as well as Zynq-7000, 7 series, Virtex-6 and Virtex-5 FPGA common clock built-in FIFOs.

Common DistributedRAM 

Common Shift Register

Common Built-in FIFO

b. The built-in FIFO primitive is only available in the Virtex-6, Virtex-5 and Virtex-4 architectures.



c. FWFT is supported for Built-in FIFOs in Zynq-7000, 7 series, Virtex-6 and Virtex-5 devices only.



(a)

Independent Block RAM 

(a)

Independent Distributed RAM 

Independent Built-in FIFO

(b)

d. For non-symmetric aspect ratios, use the block RAM implementation (feature not supported in built-in FIFO

primitive).



(c)



FIFO Generator v9.2 www.xilinx.com 17

PG057 July 25, 2012

Feature Summary

Independent Clocks: Block RAM and Distributed RAM

This implementation category allows the user to select block RAM or distributed RAM and

supports independent clock domains for write and read data accesses. Operations in the

read domain are synchronous to the read clock and operations in the write domain are

synchronous to the write clock.

The feature set supported for this type of FIFO includes non-symmetric aspect ratios

(different write and read port widths), status flags (full, almost full, empty, and almost

empty), as well as programmable full and empty flags generated with user-defined

thresholds. Optional read data count and write data count indicators provide the number of

words in the FIFO relative to their respective clock domains. In addition, optional

handshaking and error flags are available (write acknowledge, overflow, valid, and

underflow). For Zynq-7000, 7 series, Virtex-6 and Virtex-5 FPGA designs, the block RAM

FIFO configuration also supports ECC.

Independent Clocks: Zynq-7000, 7 Series, Virtex-6, Virtex-5 or Virtex-4 FPGA

Built-in FIFO

This implementation category allows the user to select the built-in FIFO available in the

Zynq-7000, 7 series, Virtex-6, Virtex-5 or Virtex-4 FPGA architecture. Operations in the read

domain are synchronous to the read clock and operations in the write domain are

synchronous to the write clock.

The feature set supported for this configuration includes status flags (full and empty) and

programmable full and empty flags generated with user-defined thresholds. In addition,

optional handshaking and error flags are available (write acknowledge, overflow, valid, and

underflow). The Zynq-7000, 7 series, Virtex-6 and Virtex-5 FPGA built-in FIFO configuration

also supports the built-in ECC feature.

Native FIFO Generator Feature Summary

Table 1-4 summarizes the supported FIFO Generator features for each clock configuration

and memory type.

Table 1-4: FIFO Configurations Summary

FIFO Feature

Independent Clocks Common Clock

Block RAM

Distributed

RAM

Built-in

FIFO

Block RAM

Distributed

RAM, Shift

Built-in

FIFO

Non-symmetric

Aspect Ratios



Symmetric

Aspect Ratios

 

Almost Full   

FIFO Generator v9.2 www.xilinx.com 18

PG057 July 25, 2012

Feature Summary

Using Block RAM FIFOs Versus Built-in FIFOs

The Built-In FIFO solutions were implemented to take advantage of logic internal to the

Built-in FIFO macro. Several features, for example, non-symmetric aspect ratios, almost full,

almost empty, and so forth were not implemented because they are not native to the macro

and require additional logic in the fabric to implement.

Benchmarking suggests that the advantages the Built-In FIFO implementations have over

the block RAM FIFOs (for example, logic resources) diminish as external logic is added to

implement features not native to the macro. This is especially true as the depth of the

implemented FIFO increases. It is strongly recommended that users requiring features not

available in the Built-In FIFOs implement their design using block RAM FIFOs.

Almost Empty   

Handshaking  

Data Count   

Programmable

Empty/Full

Thresholds



(b)

First-Word

Fall-Through

(c)

 

Synchronous

Reset



Asynchronous

Reset



(d)



(d)



(d)



DOUT Reset

Value

  

(e)e

ECC 

(f)



(f)



(f)

Embedded



(g)



(g)



(g)g

a. For applications with a single clock that require non-symmetric ports, use the independent clock configuration and

connect the write and read clocks to the same source. A dedicated solution for common clocks will be available in

a future release. Contact your Xilinx representative for more details.

b. For built-in FIFOs, the range of Programmable Empty/Full threshold is limited to take advantage of the logic internal

to the macro.

c. First-Word-Fall-Through is not supported for the shift RAM FIFOs and Virtex-4 built-in FIFOs.

d. Asynchronous reset is optional for all FIFOs built using distributed and block RAM.

e. DOUT Reset Value is supported only in Zynq-7000, 7 series, and Virtex-6 FPGA common clock built-in FIFOs.

f. ECC is only supported for the Zynq-7000, 7 series, Virtex-6 and Virtex-5 FPGAs and block RAM and built-in FIFOs.

g. Embedded register option is only supported in Zynq-7000, 7 series, Virtex-6, Virtex-5 and Virtex-4 FPGA block RAM

FIFOs, as well as Zynq-7000, 7 series, Virtex-6 and Virtex-5 FPGA common clock built-in FIFOs. See <BL

Blue>Embedded Registers in block RAM and FIFO Macros.

Table 1-4: FIFO Configurations Summary (Cont’d)

FIFO Feature

Independent Clocks Common Clock

Block RAM

Distributed

RAM

Built-in

FIFO

Block RAM

Distributed

RAM, Shift

Built-in

FIFO

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PG057 July 25, 2012

Feature Summary

Table 1-6: Write Interface Signals for FIFOs with Independent Clocks

Name Direction Description

Required

WR_CLK Input Write Clock: All signals on the write domain are synchronous to

this clock.

DIN[N:0] Input Data Input: The input data bus used when writing the FIFO.

WR_EN Input Write Enable: If the FIFO is not full, asserting this signal causes

data (on DIN) to be written to the FIFO.

FULL Output Full Flag: When asserted, this signal indicates that the FIFO is full.

Write requests are ignored when the FIFO is full, initiating a write

when the FIFO is full is not destructive to the contents of the FIFO.

Optional

WR_RST Input Write Reset: Synchronous to write clock. When asserted,

initializes all internal pointers and flags of write clock domain.

ALMOST_FULL Output Almost Full: When asserted, this signal indicates that only one

more write can be performed before the FIFO is full.

PROG_FULL Output Programmable Full: This signal is asserted when the number of

words in the FIFO is greater than or equal to the assert threshold.

It is deasserted when the number of words in the FIFO is less than

the negate threshold.

WR_DATA_COUNT [D:0] Output Write Data Count: This bus indicates the number of words written

into the FIFO. The count is guaranteed to never under-report the

number of words in the FIFO, to ensure the user never overflows

the FIFO. The exception to this behavior is when a write operation

occurs at the rising edge of WR_CLK, that write operation will

only be reflected on WR_DATA_COUNT at the next rising clock

edge.

If D is less than log2(FIFO depth)-1, the bus is truncated by

removing the least-significant bits.

WR_ACK Output Write Acknowledge: This signal indicates that a write request

(WR_EN) during the prior clock cycle succeeded.

OVERFLOW Output Overflow: This signal indicates that a write request (WR_EN)

during the prior clock cycle was rejected, because the FIFO is full.

Overflowing the FIFO is not destructive to the contents of the

FIFO.

PROG_FULL_THRESH Input Programmable Full Threshold: This signal is used to input the

threshold value for the assertion and de-assertion of the

programmable full (PROG_FULL) flag. The threshold can be

dynamically set in-circuit during reset.

The user can either choose to set the assert and negate threshold

to the same value (using PROG_FULL_THRESH), or the user can

control these values independently (using

PROG_FULL_THRESH_ASSERT and PROG_FULL_THRESH_NEGATE).

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Xilinx FIFO IP核设计与配置指南

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