STM32F411系列单片机开发关键数据手册

STM32F411

数据手册

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"STM32F411系列数据手册提供了关于STM32F411系列微控制器的详细技术规格和功能介绍，是开发者进行STM32F411产品开发的重要参考资料。" STM32F411系列是基于ARM Cortex-M4内核的32位微控制器，其主要特性包括： 1. **动态效率线性**：集成批量采集模式（Batch Acquisition Mode），优化了能源效率。 2. **核心性能**：采用ARM Cortex-M4处理器，带浮点运算单元（FPU）和自适应实时加速器（ART Accelerator），可在Flash内存中实现0等待状态执行，最高工作频率可达100MHz。内含内存保护单元，提供125 DMIPS/1.25 DMIPS/MHz的性能，并支持数字信号处理指令。 3. **内存配置**：拥有高达512KB的闪存和128KB的SRAM，满足存储程序和数据的需求。 4. **时钟、复位和电源管理**：支持1.7V至3.6V的应用电源和I/O电压范围，具备上电复位（POR）、掉电复位（PDR）、电压检测（PVD）和过压保护（BOR）。提供4至26MHz的晶体振荡器、16MHz的工厂校准内部RC振荡器以及用于RTC的32kHz校准振荡器和32kHz内部RC振荡器。 5. **低功耗模式**：运行模式下，外设关闭时每MHz消耗电流100µA；在停机模式（Flash保持在停机模式）下，快速唤醒时间的典型电流为42µA@25°C，最大值为65µA@25°C；在深度停机模式（Flash在深度电源下降模式）下，唤醒速度快，电流可低至10µA@25°C，最大不超过30µA@25°C。 6. **通信接口**：多达13种通信接口，包括USB OTG FS（全速），11个定时器，以及1个ADC，这使得STM32F411适用于多种外设连接和控制场景。这些特性使STM32F411系列微控制器适用于需要高性能计算、低功耗以及多种通信接口的嵌入式应用，如物联网设备、工业控制、音频处理、人机界面等。在实际开发中，开发者可以依据数据手册提供的详细信息，选择合适的管脚配置、时钟设置、电源管理策略，以及优化代码以充分利用其硬件资源。同时，手册还包含故障排查和安全性的相关信息，对于确保产品的稳定性和可靠性至关重要。

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Functional overview STM32F411xC STM32F411xE

16/145 DocID026289 Rev 3

3 Functional overview

3.1 ARM

Cortex

-M4 with FPU core with embedded Flash and

SRAM

The ARM

Cortex

-M4 with FPU processor is the latest generation of ARM processors for

embedded systems. It was developed to provide a low-cost platform that meets the needs of

MCU implementation, with a reduced pin count and low-power consumption, while

delivering outstanding computational performance and an advanced response to interrupts.

The ARM

Cortex

-M4 with FPU 32-bit RISC processor features exceptional code-

efficiency, delivering the high-performance expected from an ARM core in the memory size

usually associated with 8- and 16-bit devices. The processor supports a set of DSP

instructions which allow efficient signal processing and complex algorithm execution. Its

single precision FPU (floating point unit) speeds up software development by using

metalanguage development tools, while avoiding saturation.

The STM32F411xC/xE devices are compatible with all ARM tools and software.

Figure 3 shows the general block diagram of the STM32F411xC/xE.

Note: Cortex

-M4 with FPU is binary compatible with Cortex

-M3.

3.2 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-

standard ARM

Cortex

-M4 with FPU processors. It balances the inherent performance

advantage of the ARM

Cortex

-M4 with FPU over Flash memory technologies, which

normally requires the processor to wait for the Flash memory at higher frequencies.

To release the processor full 105 DMIPS performance at this frequency, the accelerator

implements an instruction prefetch queue and branch cache, which increases program

execution speed from the -bit Flash memory. Based on CoreMark benchmark, the

performance achieved thanks to the ART accelerator is equivalent to 0 wait state program

execution from Flash memory at a CPU frequency up to 100 MHz.

3.3 Batch Acquisition mode (BAM)

The Batch acquisition mode allows enhanced power efficiency during data batching. It

enables data acquisition through any communication peripherals directly to memory using

the DMA in reduced power consumption as well as data processing while the rest of the

system is in low-power mode (including the flash and ART). For example in an audio

system, a smart combination of PDM audio sample acquisition and processing from the I2S

directly to RAM (flash and ART

™ stopped) with the DMA using BAM followed by some very

short processing from flash allows to drastically reduce the power consumption of the

application. A dedicated application note (AN4515) describes how to implement the

STM32F411xC/xE BAM to allow the best power efficiency.

DocID026289 Rev 3 17/145

STM32F411xC STM32F411xE Functional overview

3.4 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to

prevent one task to accidentally corrupt the memory or resources used by any other active

task. This memory area is organized into up to 8 protected areas that can in turn be divided

up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4

gigabytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be

protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-

time operating system). If a program accesses a memory location that is prohibited by the

MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can

dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

3.5 Embedded Flash memory

The devices embed up to 512 Kbytes of Flash memory available for storing programs and

data.

To optimize the power consumption the Flash memory can also be switched off in Run or in

Sleep mode (see Section 3.18: Low-power modes). Two modes are available: Flash in Stop

mode or in DeepSleep mode (trade off between power saving and startup time, see

Table 34: Low-power mode wakeup timings(1)). Before disabling the Flash, the code must

be executed from the internal RAM.

3.6 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit

data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a software

signature during runtime, to be compared with a reference signature generated at link-time

and stored at a given memory location.

3.7 Embedded SRAM

All devices embed:

• 128 Kbytes of system SRAM which can be accessed (read/write) at CPU clock speed

with 0 wait states

3.8 Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves

(Flash memory, RAM, AHB and APB peripherals) and ensures a seamless and efficient

operation even when several high-speed peripherals work simultaneously.

DocID026289 Rev 3 19/145

STM32F411xC STM32F411xE Functional overview

3.10 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels,

and handle up to 62 maskable interrupt channels plus the 16 interrupt lines of the

Cortex

-M4 with FPU.

• Closely coupled NVIC gives low-latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Allows early processing of interrupts

• Processing of late arriving, higher-priority interrupts

• Support tail chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimum interrupt

latency.

3.11 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 21 edge-detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 81 GPIOs can be connected

to the 16 external interrupt lines.

3.12 Clocks and startup

On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The

16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy at 25 °C. The

application can then select as system clock either the RC oscillator or an external 4-26 MHz

clock source. This clock can be monitored for failure. If a failure is detected, the system

automatically switches back to the internal RC oscillator and a software interrupt is

generated (if enabled). This clock source is input to a PLL thus allowing to increase the

frequency up to 100 MHz. Similarly, full interrupt management of the PLL clock entry is

available when necessary (for example if an indirectly used external oscillator fails).

Several prescalers allow the configuration of the two AHB buses, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB

buses is 100 MHz while the maximum frequency of the high-speed APB domains is

100 MHz. The maximum allowed frequency of the low-speed APB domain is 50 MHz.

The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class

performance. In this case, the I

S master clock can generate all standard sampling

frequencies from 8 kHz to 192 kHz.

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