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FIFO Generator v13.2 www.xilinx.com 19
PG057 October 4, 2017
Chapter 1: Overview
wr_data_count [d:0]
Output
Write Data Count: This bus indicates the number of words
written into the FIFO. The count is guaranteed to never
under-report the number of words in the FIFO, to ensure you
never overflow the FIFO. The exception to this behavior is
when a write operation occurs at the rising edge of wr_clk/
clk, that write operation will only be reflected on
wr_data_count at the next rising clock edge.
If D is less than log2(FIFO depth)-1, the bus is truncated by
removing the least-significant bits.
Note:
wr_data_count is also available for UltraScale devices using
a common clock Block RAM-based FIFO when the Asymmetric Port
Width option is enabled.
wr_ack
Output
Write Acknowledge: This signal indicates that a write
request (wr_en) during the prior clock cycle succeeded.
overflow
Output
Overflow: This signal indicates that a write request (wr_en)
during the prior clock cycle was rejected, because the FIFO
is full. Overflowing the FIFO is not destructive to the
contents of the FIFO.
prog_full_thresh
Input
Programmable Full Threshold: This signal is used to input
the threshold value for the assertion and de-assertion of the
programmable full (prog_full) flag. The threshold can be
dynamically set in-circuit during reset.
You can either choose to set the assert and negate threshold
to the same value (using prog_full_thresh), or you can
control these values independently (using
prog_full_thresh_assert and prog_full_thresh_negate).
prog_full_thresh_assert
Input
Programmable Full Threshold Assert: This signal is used to
set the upper threshold value for the programmable full
flag, which defines when the signal is asserted. The
threshold can be dynamically set in-circuit during reset.
Refer to the Vivado IDE for the valid range of values
(1)
.
prog_full_thresh_negate
Input
Programmable Full Threshold Negate: This signal is used to
set the lower threshold value for the programmable full flag,
which defines when the signal is de-asserted. The threshold
can be dynamically set in-circuit during reset. Refer to
Vivado IDE for the valid range of values
(2)
.
injectsbiterr
Input
Injects a single bit error if the ECC feature is used on block
RAMs or built-in FIFO macros.
injectdbiterr
Input
Injects a double bit error if the ECC feature is used on block
RAMs or built-in FIFO macros.
wr_rst_busy Output When asserted, this signal indicates that the write domain is
in reset state.
Note:
Available only for UltraScale device built-in FIFOS.
Notes:
1. For 7 series devices using the Built-in FIFO configuration, this signal is connected to the almostfull signal of the
FIFO18E1/FIFO36E1 primitive.
2. Valid range of values shown in the IDE are the actual values even though they are grayed out for some selections.
Table 1-5: Write Interface Signals for FIFOs with Independent Clocks (Cont’d)
Name Direction Description