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首页AXU3EG开发板原理图 Zynq UltraScale+.pdf
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ALINX Confidential
www.alinx.com
Title
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AXU3EG开发板 Schematics
1.0
PAGE01 Block diagram
119Tuesday, May 26, 2020
Title
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Document Number Rev
Date: Sheet
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AXU3EG开发板 Schematics
1.0
PAGE01 Block diagram
119Tuesday, May 26, 2020
Title
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Date: Sheet
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AXU3EG开发板 Schematics
1.0
PAGE01 Block diagram
119Tuesday, May 26, 2020
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C C
B B
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ALINX Confidential
www.alinx.com
B65_L15_P
B65_L15_N
B65_L16_N
B65_L16_P
B65_L9_N
B65_L9_P
B66_L11_P
B66_L11_N
B65_L23_P
B65_L23_N
B65_L21_N
B65_L21_P
B65_L13_N
B65_L13_P
B66_L20_P
B66_L20_N
B66_L10_P
B66_L10_N
B66_L7_P
B66_L7_NB66_L12_N
B66_L12_P
B66_L5_P
B66_L5_N
B66_L2_P
B66_L2_N
B66_L6_P
B66_L6_N
B65_L20_P
B65_L20_N
B66_L3_P
B66_L3_N
B66_L1_P
B66_L1_N
B65_L12_P
B65_L12_N
B65_L18_P
B65_L18_N
B66_L4_P
B66_L4_N
B65_L8_P
B65_L8_N
B65_L14_P
B65_L14_N
B65_L7_P
B65_L7_N
B65_L17_P
B65_L17_N
B66_L8_N
B66_L8_P
B66_L13_N
B66_L13_P
B65_L10_N
B65_L10_P
B65_L11_N
B65_L11_P
B65_L5_N
B65_L5_P
B65_L1_N
B65_L1_P
B65_L4_N
B65_L4_P
B65_L2_N
B65_L2_P
B65_L3_N
B65_L3_P
B65_L24_N
B65_L24_P
B66_L9_P
B66_L9_N
B65_L6_N
B65_L6_P
B65_L19_P
B65_L19_N
B66_L15_P
B66_L15_N
B65_L22_P
B65_L22_N
B66_L16_N
B66_L16_P
FPGA_TDO
FPGA_TDI
B66_L22_N
B66_L22_P
B66_L23_N
B66_L23_P
B66_L19_N
B66_L19_P
B66_L24_N
B66_L24_P
B45_L5_N
B45_L5_P
B66_L18_N
B66_L18_P
B66_L14_P
B66_L14_N
B46_L12_N
B46_L12_P
B46_L11_P
B46_L11_N
B46_L1_N
B46_L1_P
B46_L5_N
B46_L5_P
B46_L6_N
B46_L6_P
B46_L2_N
B46_L2_P
B66_L21_N
B66_L21_P
B45_L11_N
B45_L11_P
B45_L12_P
B45_L12_N
B46_L9_N
B46_L9_P
B46_L7_N
B46_L7_P
B46_L10_N
B46_L10_P
B45_L4_N
B45_L4_P
B45_L6_N
B45_L6_P
B46_L3_N
B46_L3_P
B46_L4_N
B46_L4_P
B45_L9_N
B45_L9_P
B45_L10_N
B45_L10_P
B66_L17_P
B66_L17_N
FPGA_TMS
FPGA_TCK
505_CLK0_N
505_CLK0_P 505_CLK3_P
505_CLK3_N
505_CLK2_P
505_CLK2_N
505_CLK1_P
505_CLK1_N
505_TX3_N
505_TX3_P
505_RX3_P
505_RX3_N
505_RX1_N
505_RX1_P
505_TX2_P
505_TX2_N
505_RX0_P
505_RX0_N
505_TX0_N
505_TX0_P
505_TX1_N
505_TX1_P
505_RX2_P
505_RX2_N
PCIE_TX_P
10
PCIE_TX_N
10
FPGA_TCK
4
FPGA_TMS
4
FPGA_TDI
4
USB_SSRXN
5
USB_SSRXP
5
USB_SSTXN
5
USB_SSTXP
5
505_USB_CLKP
15
505_USB_CLKN
15
FPGA_TDO
4
PHY2_RESET
8
PHY2_RXCK
8
PHY2_MDIO
8
B46_L12_N
18
B45_L6_P
18
B46_L6_N
18
B46_L6_P
18
B46_L3_N
18
B46_L3_P
18
B46_L2_N
18
B46_L2_P
18
B46_L4_N
18
B46_L4_P
18
B46_L1_P
18
B46_L5_P
18
B46_L5_N
18
B46_L9_P
18
B46_L9_N
18
B46_L7_P
18
B46_L7_N
18
B46_L10_P
18
B46_L10_N
18
B46_L11_N
18
B46_L11_P
18
B45_L4_P
18
B46_L12_P
18
B46_L1_N
18
B45_L6_N
18
B45_L11_N
18
B45_L4_N
18
B45_L11_P
18
GT0_DP_TX_P
09
GT0_DP_TX_N
09
505_DP_CLKP
15
505_DP_CLKN
15
505_PCIE_REFCLK_P
15
505_PCIE_REFCLK_N
15
GT1_DP_TX_P
09
GT1_DP_TX_N
09
PHY2_RXD2
8
PHY2_TXCTL
8
PHY2_RXCTL
8
PHY2_MDC
8
PHY2_TXD3
8
PHY2_TXD2
8
PHY2_TXD1
8
PHY2_RXD0
8
PHY2_TXD0
8
PHY2_RXD1
8
PHY2_RXD3
8
PCIE_RX_N
10
PCIE_RX_P
10
PL_485_DE2
14
PL_485_DE1
14
B45_L9_N
18
B45_L9_P
18
B45_L5_P
18
B45_L5_N
18
B45_L12_N
18
B45_L12_P
18
PHY2_TXCK
8
MIPI_CLK_P
17
MIPI_CLK_N
17
MIPI_LAN0_N
17
MIPI_LAN0_P
17
MIPI_LAN1_N
17
MIPI_LAN1_P
17
Title
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AXU3EG开发板 Schematics
1.0
PAGE02 Connector_1
219Tuesday, May 26, 2020
Title
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Date: Sheet
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AXU3EG开发板 Schematics
1.0
PAGE02 Connector_1
219Tuesday, May 26, 2020
Title
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Document Number Rev
Date: Sheet
of
AXU3EG开发板 Schematics
1.0
PAGE02 Connector_1
219Tuesday, May 26, 2020
J1
AXK6A2337YG
2
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120
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83
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91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
122
J2
AXK6A2337YG
2
4
6
8
10
12
14
16
18
20
22
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26
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30
32
34
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104
106
108
110
112
114
116
118
120
1
3
5
7
9
11
13
15
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19
21
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25
27
29
31
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35
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93
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99
101
103
105
107
109
111
113
115
117
119
121
122
5
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4
4
3
3
2
2
1
1
D D
C C
B B
A A
ALINX Confidential
www.alinx.com
B43_L11_P
B43_L11_N
B43_L2_N
B43_L2_P
224_CLK0_N
224_CLK0_P
B44_L12_P
B44_L12_N
B44_L1_P
B44_L1_N
B43_L7_N
B43_L7_P
224_CLK1_P
224_CLK1_N
B44_L10_P
B44_L10_N
B44_L7_P
B44_L7_N
B43_L9_P
B43_L9_N
B44_L2_P
B44_L2_N
B44_L4_P
B44_L4_N
PS_POR_B
B44_L6_P
B44_L6_N
B43_L3_P
B43_L3_N
B43_L5_P
B43_L5_N
B43_L6_P
B43_L6_N
B44_L3_P
B44_L3_N
B44_L5_P
B44_L5_N
B43_L12_N
B43_L12_P
B44_L9_N
B44_L9_P
B43_L10_N
B43_L10_P
B43_L4_P
B43_L4_N
B43_L1_N
B43_L1_P
B43_L8_N
B43_L8_P
VBAT_IN
MR
B44_L8_P
B44_L8_N
B44_L11_P
B44_L11_N
PS_MIO32
PS_MIO33
PS_MIO36
PS_MIO37
PS_MIO42
PS_MIO51
PS_MIO43
PS_MIO70
PS_MIO75
PS_MIO71
PS_MIO72
PS_MIO73
PS_MIO74
PS_MIO69
PS_MIO64
PS_MIO68
PS_MIO67
PS_MIO66
PS_MIO65
PS_MIO63
PS_MIO53
PS_MIO62
PS_MIO61
PS_MIO59
PS_MIO28
PS_MIO27
PS_MIO54
PS_MIO57
PS_MIO56
PS_MIO55
PS_MIO52
PS_MIO26
PS_MIO30
PS_MODE2
PS_MODE3
PS_MODE1
PS_MODE0
PS_MIO31
PS_MIO40
PS_MIO49
PS_MIO34_SCL
PS_MIO76
PS_MIO38
PS_MIO44
PS_MIO45
PS_MIO47
PS_MIO48
PS_MIO41
PS_MIO46
PS_MIO77
PS_MIO50
PS_MIO29
PS_MIO35_SDA
PS_MIO39
PS_MIO60
PS_MIO58
PS_MIO25
PS_MIO24
224_RX3_N
224_RX3_P
224_RX2_N
224_RX2_P
224_TX3_N
224_TX3_P
224_TX2_N
224_TX2_P
224_TX1_N
224_TX1_P
224_TX0_N
224_TX0_P
224_RX0_N
224_RX0_P
224_RX1_N
224_RX1_P
+12V
+12V
+1.8V
+12V +1.8V
VCCO_65
MR
4
VBAT_IN
4
PS_IIC1_SCL
12
PS_MODE2
4
PS_MODE3
4
PS_MODE0
4
PS_MODE1
4
PS_KEY116
SD_D3
12
PHY1_MDIO
7
USB_STP
5
USB_RESET_N
5
PS_CAN2_TX
13
PHY1_MDC
7
PS_CAN2_RX
13
SD_CD
12
SD_D112
SD_D2
12
PS_CAN1_TX
13
SD_D0
12
SD_CMD
12
USB_NXT
5
USB_CLK 5
USB_DIR
5
USB_DATA2 5
USB_DATA1
5
USB_DATA0 5
USB_DATA5
5
USB_DATA6
5
USB_DATA4
5
USB_DATA3
5
PS_IIC1_SDA
12
PS_CAN1_RX
13
SD_CLK
12
PHY1_RXCK
7
PHY1_RXCTL
7
PHY1_RXD0
7
PHY1_RXD1
7
PHY1_RXD2
7
PHY1_RXD3
7
PHY1_TXCTL
7
PHY1_TXCK
7
PHY1_TXD3
7
PHY1_TXD2
7
PHY1_TXD1
7
PHY1_TXD0
7
USB_DATA7
5
PS_POR_B
7,19
MIO28_DP_HPD
09
MIO27_DP_AUX_OUT
09
MIO29_DP_OE
09
MIO30_DP_AUX_IN
09
PS_LED1
16
B43_L2_P
18
B43_L2_N
18
B44_L8_N
18
B44_L6_P
18
B44_L8_P
18
B44_L9_P
18
B44_L9_N
18
B44_L11_P
18
B44_L11_N
18
B43_L10_P
18
B44_L12_P
18
B43_L10_N
18
B44_L12_N
18
B43_L12_P
18
B43_L12_N
18
B44_L3_P
18
B44_L3_N
18
B44_L7_P
18
B44_L10_P
18
B43_L6_P
18
B43_L7_N
18
B44_L10_N
18
B44_L7_N
18
B43_L6_N
18
B44_L6_N
18
B43_L7_P
18
B43_L8_P
18
PS_UART0_TX
11
PS_UART0_RX
11
B43_L8_N 18
PCIE_RSTn_MIO37
10
PS_MIO36
10
B44_L5_P
18
B44_L5_N
18
B44_L1_P
18
B44_L1_N
18
FAN_PWM 19
B44_L2_P 18
B44_L2_N
18
PL_KEY1
16
PL_LED1
16
PL_485_TXD1
14
PL_485_TXD2
14
PL_485_RXD2
14
PL_485_RXD1
14
PL_UART_RX
11
PL_UART_TX
11
CAM_CLK
17
CAM_GPIO
17
CAM_SCL
17
CAM_SDA
17
Title
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Document Number Rev
Date: Sheet
of
AXU3EG开发板 Schematics
1.0
PAGE03 Connector_2
319Tuesday, May 26, 2020
Title
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Document Number Rev
Date: Sheet
of
AXU3EG开发板 Schematics
1.0
PAGE03 Connector_2
319Tuesday, May 26, 2020
Title
Size
Document Number Rev
Date: Sheet
of
AXU3EG开发板 Schematics
1.0
PAGE03 Connector_2
319Tuesday, May 26, 2020
J4
AXK6A2337YG
2
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6
8
10
12
14
16
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20
22
24
26
28
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32
34
36
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58
60
62
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76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
1
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7
9
11
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15
17
19
21
23
25
27
29
31
33
35
37
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41
43
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83
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91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
122
J3
AXK6A2337YG
2
4
6
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105
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109
111
113
115
117
119
121
122
C285
10uF 25V
C262
10uF 25V
C282
10uF 25V
C261
10uF 25V
C263
10uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ALINX Confidential
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MODE[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1110
1000
1001
BOOT MODE Descritpion
PS JTAG
Quad_SPI(24b)
Quad_SPI(32b)
SD0(2.0)
NAND
SD1(2.0)
eMMC(1.8V)
USB0(2.0)
PJTAG(MIO #0)
PJTAG(MIO #1)
SD1 LS(3.0)
PS JTAG Interface
24-Bit addresssing(QSPI24)
32-Bit addresssing(QSPI32)
SD2.0
SD2.0
Requires 8-bit data bus width
eMMC version 4.5 at 1.8V
USB 2.0 only
PJTAG connection 0 option
PJTAG connection 1 option
SD 3.0
JTAG Connector
VBAT_IN
MR
PS_MODE3
PS_MODE1
PS_MODE2
PS_MODE0
FPGA_TDO
FPGA_TMS
FPGA_TDI
FPGA_TCK
FPGA_TCK
FPGA_TDO
FPGA_TMS
FPGA_TDI
+3.3V
+3.3V
+3.3V
+3.3V +3.3V +3.3V +3.3V
+3.3V
VBAT_IN
3
MR
3
PS_MODE3
3
PS_MODE1
3
PS_MODE2
3
PS_MODE0
3
FPGA_TCK
2
FPGA_TMS
2
FPGA_TDI
2
FPGA_TDO
2
Title
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Document Number Rev
Date: Sheet
of
AXU3EG开发板 Schematics
1.0
Page04 JTAG
419Tuesday, May 26, 2020
Title
Size
Document Number Rev
Date: Sheet
of
AXU3EG开发板 Schematics
1.0
Page04 JTAG
419Tuesday, May 26, 2020
Title
Size
Document Number Rev
Date: Sheet
of
AXU3EG开发板 Schematics
1.0
Page04 JTAG
419Tuesday, May 26, 2020
J5
HEADER 5X2
2
4
6
8
10
1
3
5
7
9
C5
4.7uF
D29
BAT54S
R45
10K 1%
KEY7
Button
P1
1
P2
2
P4
4
P3
3
R4 4.7K
D28
BAT54S
R6 220
D27
BAT54S
SW1
SW DIP-4
R5 220
R3 4.7K
R16
10K 1%
R62
10K 1%
C6
100uF
R2 4.7K
BT1
BATTERY_4
R8 220
R61
10K 1%
R1 4.7K
R46
10K 1%
D30
BAT54S
R7 220
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