Revision 2.1
Document Conventions
The following name and usage conventions are used in this document:
asserted, deasserted The terms asserted and deasserted refer to the
globally visible state of the signal on the clock edge,
not to signal transitions.
edge, clock edge The terms edge and clock edge refer to the rising edge
of the clock. On the rising edge of the clock is the
only time signals have any significance on the PCI
bus.
# A # symbol at the end of a signal name indicates that
the signal’s active state occurs when it is at a low
voltage. The absence of a # symbol indicates that the
signal is active at a high voltage.
reserved The contents or undefined states or information are
not defined at this time. Using any reserved area in
the PCI specification is not permitted. All areas of
the PCI specification can only be changed according
to the by-laws of the PCI Special Interest Group. Any
use of the reserved areas of the PCI specification will
result in a product that is not PCI-compliant. The
functionality of any such product cannot be
guaranteed in this or any future revision of the PCI
specification.
signal names Signal names are indicated with this bold font. At
the first mention of a signal, the full signal name
appears with its abbreviation in parentheses. After its
first mention, the signal is referred to by its
abbreviation.
signal range A signal name followed by a range enclosed in
brackets, for example AD[31::00], represents a range
of logically related signals. The first number in the
range indicates the most significant bit (msb) and the
last number indicates the least significant bit (lsb).
implementation notes Implementation notes are enclosed in a box. They are
not part of the PCI specification and are included for
clarification and illustration only.
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