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AN619-si5351寄存器查询手册和计算公式.pdf
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Rev. 0.6 9/15 Copyright © 2015 by Silicon Laboratories AN619
AN619
Manually Generating an Si5351 Register Map
1. Introduction
The Si5351 is a highly flexible and configurable clock generator and VCXO. A block diagram of the Si5351
programmable clock IC is shown in Figure 1. To support this flexibility, Silicon Labs has created ClockBuilder
Desktop to create register maps automatically and easily for a given configuration. Since programming with
ClockBuilder Desktop may not always be well suited for every system’s requirements, this document presents the
procedures and equations for determining a complete register set from a frequency plan. Section 2 highlights the
overall frequency plan algorithm, and sections 3 and beyond detail all the necessary register calculations.
Figure 1. Generalized Si5351 Block Diagram
Figure 1 is a generalized block diagram of the Si5351. The Si5351 is available in three variants:
Si5351A—XTAL only device.
Si5351B—XTAL+VCXO.
Si5351C—XTAL + CLKIN.
If spread spectrum is turned on, it is supported by PLLA. VCXO functionality (Si5351B devices only) is supported
by PLLB.
AN619
2 Rev. 0.6
2. Conceptualizing a Frequency Plan
The device consists of two PLLs—PLLA and PLLB. Each PLL consists of a Feedback Multisynth used to generate
an intermediate VCO frequency in the range of 600 to 900 MHz. Either of these two VCO frequencies can be
divided down by the individual output Multisynth dividers to generate a Multisynth frequency between 500 kHz and
200 MHz. Additionally, the R dividers can be used to generate any output frequency down to 2.5 kHz. The
relationship between the VCO and output frequencies is given below.
Use the steps in the sections below to draw out a conceptual frequency plan map.
2.1. PLL Selection
If spread spectrum is not enabled, either of the two PLLs may be used as the source for any outputs of the
Si5351A. If both XTAL and CLKIN input options are used simultaneously (Si5351C only), then one PLL must be
reserved for use with CLKIN and one for use with the XTAL.
Note: PLLA must be used for any spread spectrum-enabled outputs. PLLB must be used for any VCXO outputs.
2.1.1. Selecting the Proper VCO Frequencies and Divide Ratios
The general criteria below may be used to set the VCO frequencies. This is a general model, and individual
applications may require some modification.
1. Valid Multisynth divider ratios are 4, 6, 8, and any fractional value between 8 + 1/1,048,575 and 900 + 0/1.
This means that if any output is greater than 112.5 MHz (900 MHz/8), then this output frequency sets one
of the VCO frequencies.
2. For the frequencies where jitter is a concern make the output Multisynth divide ratio an integer. If possible,
make both output and feedback Multisynth ratios integers.
3. Once criteria 1 and 2 are satisfied, try to select as many integer output Multisynth ratios as possible.
2.2. Output Clock Pin Assignment (Optional)
Some customers may wish to have full control of output clock pin assignment. The guidelines below may be used
to assign clocks to pins on the device.
1. Equal output frequencies should share a VDDO bank (e.g., CLOK0&1, CLK2&3, etc.) whenever possible in
order to ensure minimal jitter due to PCB crosstalk.
2. Isolate unique output frequencies on individual VDDO bank if possible. For example, if the four outputs are
25 MHz, 25 MHz, 27 MHz, and 74.25 MHz, then place them on CLK0, CLK1, CLK2, and CLK4,
respectively.
3. Otherwise, use all necessary CLK channels based on the required frequency plan.
Note: The only valid divide ratios for CLK6 and CLK7 Multisynth dividers are even integers between 6 and 254 inclusive. This
may limit the two VCO frequencies if all 8 output clocks are used.
fout
x
fvco
Multisynth
x
R
x
---------------------------------------------
=
AN619
Rev. 0.6 3
3. Configuring Input and PLL Register Parameters (Synthesis Stage 1)
This section describes register parameters related to the input reference and the two PLLs.
3.1. PLL Input Source
The input source for each PLL must be selected. For the A and B devices, the only possible source is the XTAL,
but for the C device, each PLL can be synchronized to either an XTAL or a CMOS clock on the CLKIN pin.
3.1.1. XTAL Source
If the source for the PLL is a crystal, PLLx_SRC must be set to 0 in register 15. XTAL_CL[1:0] must also be set to
match the crystal load capacitance (see register 183).
3.1.2. CMOS Clock Source
If a PLL needs to be synchronized to a CMOS clock, PLLx_SRC must be 1. The input frequency range of the PLL
is 10 to 40 MHz. If CLKIN is > 40 MHz, the CLKIN input divider must be used to bring the PLL input within the 10–
40 MHz range. See CLKIN_DIV[1:0], register bits 15 [7:6].
3.2. Feedback Multisynth Divider Equations
Once the input source for each PLL and (if necessary) CLKIN_DIV are determined, the two VCO frequencies
selected in Section 2 above can be generated using the following equations. Each feedback divider essentially
multiplies the source frequency such that
and/or
The fractional ratio
has a valid range of 15 + 0/1,048,575 and 90 +0/1,048,575 and is represented in the Si5351 register space using
the equations below.
In the equations above, x is used to represent MSNA and MSNB, the PLLA and PLLB Multisynth dividers
respectively. The equations above must be repeated for Multisynths NA and NB. As mentioned earlier in Section
“2.1. PLL Selection”, spread spectrum is only supported by PLLA, and the VCXO functionality is only supported by
PLLB. When using the VCXO function, set the MSNB divide ratio a + b/c such that c = 106. This must be taken into
consideration when configuring a frequency plan.
f
VCO
f
XTAL
a
b
c
---
+
=
f
VCO
f
CLKIN
CLKIN_DIV
---------------------------------
a
b
c
---
+
=
a
b
c
---
+
MSNx_P1 17:0128 a Floor 128
b
c
---
+ 512–=
MSNx_P2 19:0128 b c Floor 128
b
c
---
–=
MSNx_P3 19:0c=
AN619
4 Rev. 0.6
3.2.1. Integer Divide Values (FBx_INT)
If a + b/c is an even integer, integer mode may be enabled for PLLA or PLLB by setting parameter FBA_INT or
FBB_INT respectively. In most cases setting this bit will improve jitter when using even integer divide values.
Whenever spread spectrum is enabled, FBA_INT must be set to 0.
3.3. Miscellaneous PLL Parameters
Set PLLA_CL=2
Set PLLB_CL=2
AN619
Rev. 0.6 5
4. Configuring the Output Register Parameters
This section covers the Multisynth and output driver settings necessary for each output. As shown in Figure 2, one
of the two VCO frequencies is divided down by each Multisynth divider. This is followed by an output driver state.
See “4.2. Output Driver Settings”.
Figure 2. Detailed Dividers and Output Drivers Block Diagram
÷R7
÷R6
÷R5
÷R4
÷R3
÷R2
÷R1
÷R0
Multisynth0
÷M0
Multisynth1
÷M1
Multisynth6
÷M6*
Multisynth7
÷M7*
Multisynth5
÷M5
Multisynth3
÷M3
Multisynth4
÷M4
Multisynth2
÷M2
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
M1
M0
M6
M5
M4
M3
M2
M7
M0
M0
M4
M4
M4
M0
XO
XO
XO
XO
XO
XO
XO
XO
VCOA
VCOB
VCOA
VCOB
VCOA
VCOB
VCOA
VCOB
VCOA
VCOB
VCOA
VCOB
VCOA
VCOB
VCOA
VCOB
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
PLLA
N
A
PLLB
N
B
XO
CLKIN
XO
CLKIN
* Multisynth 6 and 7 divide ratios can only be even integers between 6 and 254.
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