Creating and Packaging Custom IP 16
UG1118 (v2019.2) March 2, 2020 www.xilinx.com
Chapter 2: IP Packaging Basics
Packaging a Design with Global Include Files
The Vivado IDE supports designating Verilog or Verilog Header files as global `include
files to process before any other sources.
Note:
This feature is not supported when packaging a custom IP.
After packaging, the Vivado tool treats global `include files as standard Verilog or Verilog
Header files.
To package a design that uses global ‘include files, you must modify the HDL to place the
`include statement at the top of any Verilog source file that references content from
another Verilog or Verilog header file.
Constraints Requirements
The IP packager supports constraints files (XDC) along with RTL files. The following are the
supported XDC file types:
• XDC to be used during synthesis and implementation (default)
• XDC to be used only during implementation
• XDC for use only during out-of-context (OOC) synthesis
This section describes the following concepts:
• Managing Out-of-Context Constraints
• Processing Order of Constraints
For more details on IP constraints, see Vivado Design Suite User Guide: Using Constraints
(UG903) [Ref 12], and for constraints in general see Vivado Design Suite User Guide:
Synthesis (UG901) [Ref 11].
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