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arm smmu spec. A System Memory Management Unit (SMMU) performs a task that is analogous to that of an MMU in a PE, translating addresses for DMA requests from system I/O devices before the requests are passed into the system interconnect. It is active for DMA only. Traffic in the other direction, from the system or PE to the device, is managed by other means – for example, the PE MMUs.
Copyright © 2016-2019 Arm Limited or its affiliates. All rights reserved.
Document number: IHI 0070C.a
System Memory Management Unit
SMMU architecture versions 3.0, 3.1 and 3.2
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System Memory Management Unit Architecture Specification
Copyright © 2016-2019 Arm Limited or its affiliates. All rights reserved.
Changes made to this document:
Date Issue Confidentiality Change
15 September 2016 A Non-Confidential First release
14 June 2017 B Non-Confidential Amendments and clarifications.
16 March 2018 C Non-confidential Update with SMMUv3.2 architecture. Further
amendments and clarifications.
18 July 2019 C.a Non-confidential Amendments and clarifications.
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1 ABOUT THIS DOCUMENT 14
1.1 References 14
1.2 Terms and abbreviations 14
1.3 Document Scope 18
2 INTRODUCTION 19
2.1 History 19
2.2 SMMUv3.0 features 20
2.3 SMMUv3.1 features 21
2.4 SMMUv3.2 features 21
2.5 Permitted implementation of subsets of SMMUv3.x and SMMUv3.(x+1) architectural features 22
2.6 System placement 23
3 OPERATION 26
3.1 Software interface 26
3.2 Stream numbering 26
3.3 Data structures and translation procedure 27
3.3.1 Stream Table lookup 28
3.3.2 StreamIDs to Context Descriptors 30
3.3.3 Configuration and Translation lookup 35
3.3.4 Transaction attributes: incoming, two-stage translation and overrides 37
3.3.5 Translation table descriptors 38
3.4 Address sizes 38
3.4.1 Input address size and Virtual Address size 41
3.4.2 Address alignment checks 42
3.4.3 Address sizes of SMMU-originated accesses 42
3.5 Command and Event queues 44
3.5.1 SMMU circular queues 44
3.5.2 Queue entry visibility semantics 48
3.5.3 Event queue behavior 48
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3.5.4 Definition of event record write “Commit” 49
3.5.5 Event merging 49
3.6 Structure and queue ownership 50
3.7 Programming registers 51
3.8 Virtualization 51
3.9 Support for PCI Express, PASIDs, PRI and ATS 51
3.9.1 ATS Interface 52
3.9.2 Changing ATS configuration 59
3.10 Support for two Security states 60
3.10.1 Secure State Determination (SSD) 61
3.10.2 Secure commands, events and configuration 62
3.10.3 Secure EL2 and support for Secure stage 2 translation 64
3.11 Reset, Enable and initialization 65
3.12 Fault models, recording and reporting 68
3.12.1 Terminate model 71
3.12.2 Stall model 71
3.12.3 Considerations for client devices using the Stall fault model 75
3.12.4 Virtual Memory paging with SMMU 75
3.12.5 Combinations of fault configuration with two stages 76
3.13 Translation table entries and Access/Dirty flags 78
3.13.1 Software update of flags 78
3.13.2 Access flag hardware update 79
3.13.3 Dirty flag hardware update 80
3.13.4 HTTU behavior summary 81
3.13.5 HTTU with two stages of translation 81
3.13.6 ATS, PRI and translation table flag update 82
3.13.7 Hardware flag update for Cache Maintenance Operations and Destructive Reads 84
3.14 Speculative accesses 84
3.15 Coherency considerations and memory access types 85
3.15.1 Client devices 86
3.16 Embedded implementations 86
3.16.1 Changes to structure and queue storage behavior when fixed/preset 87
3.17 TLB tagging, VMIDs, ASIDs and participation in broadcast TLB maintenance 88
3.17.1 The Global flag in the Translation Table Descriptor 91
3.17.2 Broadcast TLB maintenance from Armv8-A PEs with EL3 in AArch64 92
3.17.3 Broadcast TLB maintenance from ARMv7-A PEs or Armv8-A PEs with EL3 using AArch32 93
3.17.4 Broadcast TLB maintenance in mixed AArch32 and AArch64 systems and with mixed ASID or VMID
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