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IMX6ULL

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i.MX 6ULL Applications Processor

Reference Manual

Document Number: IMX6ULLRM

Rev. 1, 11/2017

Contents

Section number Title Page

Chapter 1

Introduction

1.1 About This Document...................................................................................................................................................159

1.1.1 Audience.................................................................................................................................................... 159

1.1.2 Organization...............................................................................................................................................159

1.1.3 Suggested Reading.....................................................................................................................................160

1.1.3.1 General Information...............................................................................................................160

1.1.3.2 Related Documentation..........................................................................................................160

1.1.4 Conventions............................................................................................................................................... 160

1.1.5 Register Access..........................................................................................................................................162

1.1.5.1 Register Diagram Field Access Type Legend........................................................................162

1.1.5.2 Register Macro Usage............................................................................................................163

1.1.6 Signal Conventions.................................................................................................................................... 164

1.1.7 Acronyms and Abbreviations.....................................................................................................................164

1.2 Introduction...................................................................................................................................................................167

1.3 Target Applications.......................................................................................................................................................167

1.4 Features.........................................................................................................................................................................167

1.5 Architectural Overview.................................................................................................................................................171

1.5.1 Simplified Block Diagram......................................................................................................................... 171

1.5.2 Architectural Partitioning...........................................................................................................................172

1.5.3 Endianness Support....................................................................................................................................174

1.5.4 Memory Interfaces..................................................................................................................................... 174

Chapter 2

Memory Maps

2.1 Memory system overview.............................................................................................................................................175

2.2 ARM Platform Memory Map....................................................................................................................................... 175

2.3 DMA memory map.......................................................................................................................................................181

Chapter 3

i.MX 6ULL Applications Processor Reference Manual, Rev. 1, 11/2017

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Section number Title Page

Interrupts and DMA Events

3.1 Overview.......................................................................................................................................................................183

3.2 Cortex A7 interrupts..................................................................................................................................................... 183

3.3 SDMA event mapping.................................................................................................................................................. 188

Chapter 4

External Signals and Pin Multiplexing

4.1 Overview.......................................................................................................................................................................191

4.1.1 Muxing Options......................................................................................................................................... 191

Chapter 5

Fusemap

5.1 Boot Fusemap............................................................................................................................................................... 215

5.2 Lock Fusemap...............................................................................................................................................................226

5.3 Fusemap Descriptions Table.........................................................................................................................................227

Chapter 6

External Memory Controllers

6.1 Overview.......................................................................................................................................................................235

6.2 Multi-mode DDR controller (MMDC) overview and feature summary...................................................................... 235

6.3 EIM-PSRAM/NOR flash controller overview..............................................................................................................236

6.3.1 EIM features...............................................................................................................................................236

6.3.2 EIM boot scenarios.................................................................................................................................... 237

6.3.3 EIM boot configuration..............................................................................................................................237

6.3.4 OneNAND requirements............................................................................................................................238

Chapter 7

System Debug

7.1 Overview.......................................................................................................................................................................239

7.2 Chip and ARM Platform Debug Architecture.............................................................................................................. 239

7.2.1 Debug Features.......................................................................................................................................... 240

7.2.2 Debug system components.........................................................................................................................240

7.2.2.1 AMBA Trace Bus (ATB).......................................................................................................241

7.2.2.2 ATB replicator....................................................................................................................... 241

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Section number Title Page

7.2.2.3 Embedded Cross Triggering.................................................................................................. 241

7.2.2.3.1 Cross-Trigger Matrix (CTM)..........................................................................242

7.2.2.3.2 Cross-Trigger Interface (CTI).........................................................................243

7.2.2.4 Debug Access Port (DAP)..................................................................................................... 243

7.2.3 Chip-Specific SJC Features....................................................................................................................... 244

7.2.3.1 JTAG Disable Mode.............................................................................................................. 244

7.2.3.2 JTAG ID.................................................................................................................................244

7.2.4 System JTAG Controller - SJC..................................................................................................................244

7.2.5 System JTAG controller main features......................................................................................................245

7.2.6 SJC TAP Port.............................................................................................................................................245

7.2.7 SJC main blocks.........................................................................................................................................245

7.3 Smart DMA (SDMA) core............................................................................................................................................246

7.3.1 SDMA On Chip Emulation Module (OnCE) Feature Summary............................................................... 246

7.3.1.1 Other SDMA Debug Functionality........................................................................................247

7.3.1.2 SDMA ROM Patching...........................................................................................................248

7.4 Miscellaneous............................................................................................................................................................... 248

7.4.1 Clock/Reset/Power.....................................................................................................................................248

7.5 Supported tools............................................................................................................................................................. 248

Chapter 8

System Boot

8.1 Overview.......................................................................................................................................................................249

8.2 Boot modes................................................................................................................................................................... 250

8.2.1 Boot mode pin settings...............................................................................................................................251

8.2.2 High-level boot sequence...........................................................................................................................251

8.2.3 Boot From Fuses mode (BOOT_MODE[1:0] = 00b)................................................................................252

8.2.4 Serial Downloader......................................................................................................................................253

8.2.5 Internal Boot mode (BOOT_MODE[1:0] = 0b10).................................................................................... 255

8.2.6 Boot security settings.................................................................................................................................255

8.3 Device configuration.....................................................................................................................................................256

i.MX 6ULL Applications Processor Reference Manual, Rev. 1, 11/2017

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