JEDEC Standard No. 235A
Page 1
HIGH BANDWIDTH MEMORY (HBM) DRAM
(From JEDEC Board Ballot JCB-15-54, formulated under the cognizance of the JC-42.3 Subcommittee on
DRAM Memories, under item number 1797.99F, Rev. 1.42.)
1Scope
The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is
divided into independent channels. Each channel is completely independent of one another. Channels are
not necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achieve
high-speed, low-power operation. The HBM DRAM uses differential clock CK_t/CK_c. Commands are
registered at the rising edge of CK_t, CK_c. Each channel interface maintains a 128b data bus operating at
DDR data rates.
2Features
· 2n prefetch architecture with 256 bits per memory read and write access
· BL = 2 and 4
· 128 DQ width + Optional ECC pin support/channel
· Legacy Mode and Pseudo Channel Mode Operation; (64 DQ width for Pseudo Channel Mode)
· Differential clock inputs (CK_t/CK_c)
· DDR commands entered on each positive CK_t, CK_c edge. Row Activate commands require two
cycles. All other commands are one cycle command.
· Semi-independent Row & Column Command Interfaces allowing Activates/Precharges to be
issued in parallel with Read/Writes.
· Data referenced to strobes RDQS_t/RDQS_c and WDQS_t/WDQS_c. 1 strobe pair per DWORD.
· Up to 8 channels/stack
· 8 or 16 banks per channel; varies by device density/channel
· Bank Grouping supported
· 2K or 4K Bytes per page; varies by device density/channel
· DBIac support configurable via MRS
· Data mask for masking WRITE data per byte
· Self Refresh Modes
· I/O voltage 1.2 V
· DRAM core voltage 1.2 V, independent of I/O voltage
· Channel density of 1 Gb to 32 Gb
· Unterminated data/address/cmd/clk interfaces
· Temperature sensor with 3-bit encoded range output
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