Everest Semiconductor Confidential ES7243E
Revision 2.0 6 June 2019
Latest datasheet: www.everest-semi.com
or info@everest-semi.com
3. CLOCK MODES AND SAMPLING FREQUENCIES
The device supports standard audio clocks (64Fs, 128Fs, 256Fs, 384Fs, 512Fs, etc), USB clocks
(12/24 MHz), and some common non standard audio clocks (25 MHz, 26 MHz, etc).
The device can work either in master clock mode or slave clock mode. In slave mode, LRCK and
SCLK are supplied externally, and LRCK and SCLK must be synchronously derived from the
system clock with specific rates. In master mode, LRCK and SCLK are derived internally from
device master clock.
4. MICRO-CONTROLLER CONFIGURATION INTERFACE
The device supports standard I
2
C micro-controller configuration interface. External micro-
controller can completely configure the device through writing to internal configuration
registers.
I
2
C interface is a bi-directional serial bus that uses a serial data line (CDATA) and a serial clock
line (CCLK) for data transfer. The timing diagram for data transfer of this interface is given in
Figure 1a and Figure 1b. Data are transmitted synchronously to CCLK clock on the CDATA line on
a byte-by-byte basis. Each bit in a byte is sampled during CCLK high with MSB bit being
transmitted firstly. Each transferred byte is followed by an acknowledge bit from receiver to pull
the CDATA low. The transfer rate of this interface can be up to 400 kbps.
A master controller initiates the transmission by sending a “start” signal, which is defined as a
high-to-low transition at CDATA while CCLK is high. The first byte transferred is the slave address.
It is a seven-bit chip address followed by a RW bit. The chip address must be 0010 x, where x
equals AD2 AD1 AD0. The RW bit indicates the slave data transfer direction. Once an
acknowledge bit is received, the data transfer starts to proceed on a byte-by-byte basis in the
direction specified by the RW bit. The master can terminate the communication by generating a
“stop” signal, which is defined as a low-to-high transition at CDATA while CCLK is high.
In I
2
C interface mode, the registers can be written and read. The formats of “write” and “read”
instructions are shown in Table 1 and Table 2. Please note that, to read data from a register, you
must set R/W bit to 0 to access the register address and then set R/W to 1 to read data from the
register.
Table 1 Write Data to Register in I
2
C Interface Mode
Chip Address R/W Register Address Data to be written
start
0010 AD2 AD1 AD0
0
ACK
RAM
ACK
DATA
ACK
Stop
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