MT29F16G08ABABA_nandflash_美光料号归码规则

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NAND Flash Memory

MT29F16G08ABABA, MT29F32G08AFABA, MT29F64G08A[J/K/M]ABA,

MT29F128G08AUABA, MT29F16G08ABCBB, MT29F32G08AECBB,

MT29F64G08A[K/M]CBB, MT29F128G08AUCBB

Features

• Open NAND Flash Interface (ONFI) 2.1-compliant

• Single-level cell (SLC) technology

• Organization

– Page size x8: 4320 bytes (4096 + 224 bytes)

– Block size: 128 pages (512K +28K bytes)

– Plane size: 2 planes x 2048 blocks per plane

– Device size: 16Gb: 4096 blocks;

32Gb: 8192 blocks;

64Gb: 16,384 blocks;

128Gb: 32,768 blocks

• Synchronous I/O performance

– Up to synchronous timing mode 4

– Clock rate: 12ns (DDR)

– Read/write throughput per pin: 166 MT/s

• Asynchronous I/O performance

– Up to asynchronous timing mode 4

–

RC/

WC: 25ns (MIN)

• Array performance

– Read page: 25μs (MAX)

– Program page: 230μs (TYP)

– Erase block: 700μs (TYP)

• Operating Voltage Range

–V

: 2.7–3.6V

–V

CCQ

: 1.7–1.95V, 2.7–3.6V

• Command set: ONFI NAND Flash Protocol

• Advanced Command Set

– Program cache

– Read cache sequential

– Read cache random

– One-time programmable (OTP) mode

– Multi-plane commands

– Multi-LUN operations

– Read unique ID

– Copyback

• First block (block address 00h) is valid when ship-

ped from factory. For minimum required ECC, see

Error Management (page 110).

• RESET (FFh) required as first command after pow-

er-on

• Operation status byte provides software method for

detecting

– Operation completion

– Pass/fail condition

– Write-protect status

• Data strobe (DQS) signals provide a hardware meth-

od for synchronizing data DQ in the synchronous

interface

• Copyback operations supported within the plane

from which data is read

• Quality and reliability

– Data retention: 10 years

– Endurance: 100,000 PROGRAM/ERASE cycles

• Operating temperature:

– Commercial: 0°C to +70°C

– Industrial (IT): –40ºC to +85ºC

• Package

– 52-pad LGA

– 48-pin TSOP

– 100-ball BGA

Note:

1. The ONFI 2.1 specification is available at

www.onfi.org.

Micron Confidential and Proprietary

16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND

Features

PDF: CCM005-816717818-10495

Rev. F 1/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

Contents

Important Notes and Warnings ......................................................................................................................... 9

General Description ....................................................................................................................................... 10

Asynchronous and Synchronous Signal Descriptions ....................................................................................... 10

Signal Assignments ......................................................................................................................................... 12

Package Dimensions ....................................................................................................................................... 16

Architecture ................................................................................................................................................... 21

Device and Array Organization ........................................................................................................................ 22

Bus Operation – Asynchronous Interface ......................................................................................................... 30

Asynchronous Enable/Standby ................................................................................................................... 30

Asynchronous Bus Idle ............................................................................................................................... 30

Asynchronous Pausing Data Input/Output .................................................................................................. 31

Asynchronous Commands .......................................................................................................................... 31

Asynchronous Addresses ............................................................................................................................ 32

Asynchronous Data Input ........................................................................................................................... 33

Asynchronous Data Output ......................................................................................................................... 34

Write Protect .............................................................................................................................................. 35

Ready/Busy# .............................................................................................................................................. 35

Bus Operation – Synchronous Interface ........................................................................................................... 40

Synchronous Enable/Standby ..................................................................................................................... 41

Synchronous Bus Idle/Driving .................................................................................................................... 41

Synchronous Pausing Data Input/Output .................................................................................................... 42

Synchronous Commands ............................................................................................................................ 42

Synchronous Addresses .............................................................................................................................. 43

Synchronous DDR Data Input ..................................................................................................................... 44

Synchronous DDR Data Output .................................................................................................................. 45

Write Protect .............................................................................................................................................. 47

Ready/Busy# .............................................................................................................................................. 47

Device Initialization ....................................................................................................................................... 48

Activating Interfaces ....................................................................................................................................... 50

Activating the Asynchronous Interface ........................................................................................................ 50

Activating the Synchronous Interface .......................................................................................................... 50

Command Definitions .................................................................................................................................... 52

Reset Operations ............................................................................................................................................ 54

RESET (FFh) ............................................................................................................................................... 54

SYNCHRONOUS RESET (FCh) .................................................................................................................... 55

Identification Operations ................................................................................................................................ 56

READ ID (90h) ............................................................................................................................................ 56

READ ID Parameter Tables .............................................................................................................................. 57

Configuration Operations ............................................................................................................................... 58

SET FEATURES (EFh) .................................................................................................................................. 58

GET FEATURES (EEh)

................................................................................................................................. 59

READ PARAMETER PAGE (ECh) ...................................................................................................................... 63

Parameter Page Data Structure Tables ............................................................................................................. 64

READ UNIQUE ID (EDh) ................................................................................................................................ 72

Status Operations ........................................................................................................................................... 74

READ STATUS (70h) ................................................................................................................................... 75

READ STATUS ENHANCED (78h) ................................................................................................................ 76

Column Address Operations ........................................................................................................................... 77

CHANGE READ COLUMN (05h-E0h) .......................................................................................................... 77

CHANGE READ COLUMN ENHANCED (06h-E0h) ....................................................................................... 78

Micron Confidential and Proprietary

16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND

Features

PDF: CCM005-816717818-10495

Rev. F 1/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

CHANGE WRITE COLUMN (85h) ................................................................................................................ 79

CHANGE ROW ADDRESS (85h) ................................................................................................................... 80

Read Operations ............................................................................................................................................. 82

READ MODE (00h) ..................................................................................................................................... 84

READ PAGE (00h-30h) ................................................................................................................................ 85

READ PAGE CACHE SEQUENTIAL (31h) ...................................................................................................... 86

READ PAGE CACHE RANDOM (00h-31h) .................................................................................................... 87

READ PAGE CACHE LAST (3Fh) .................................................................................................................. 89

READ PAGE MULTI-PLANE (00h-32h) ......................................................................................................... 90

Program Operations ....................................................................................................................................... 92

PROGRAM PAGE (80h-10h) ......................................................................................................................... 92

PROGRAM PAGE CACHE (80h-15h) ............................................................................................................. 94

PROGRAM PAGE MULTI-PLANE (80h-11h) ................................................................................................. 96

Erase Operations ............................................................................................................................................ 98

ERASE BLOCK (60h-D0h) ............................................................................................................................ 98

ERASE BLOCK MULTI-PLANE (60h-D1h) .................................................................................................... 99

Copyback Operations .................................................................................................................................... 100

COPYBACK READ (00h-35h) ...................................................................................................................... 101

COPYBACK PROGRAM (85h–10h) .............................................................................................................. 102

COPYBACK READ MULTI-PLANE (00h-32h) ............................................................................................... 102

COPYBACK PROGRAM MULTI-PLANE (85h-11h) ....................................................................................... 103

One-Time Programmable (OTP) Operations ................................................................................................... 104

PROGRAM OTP PAGE (80h-10h) ................................................................................................................ 105

PROTECT OTP AREA (80h-10h) .................................................................................................................. 106

READ OTP PAGE (00h-30h) ........................................................................................................................ 107

Multi-Plane Operations ................................................................................................................................. 108

Multi-Plane Addressing ............................................................................................................................. 108

Interleaved Die (Multi-LUN) Operations ......................................................................................................... 108

Error Management ........................................................................................................................................ 110

Output Drive Impedance ............................................................................................................................... 111

AC Overshoot/Undershoot Specifications ....................................................................................................... 114

Synchronous Input Slew Rate ......................................................................................................................... 115

Output Slew Rate ........................................................................................................................................... 116

Electrical Specifications ................................................................................................................................. 117

Electrical Specifications – DC Characteristics and Operating Conditions (Asynchronous) ................................. 119

Electrical Specifications – DC Characteristics and Operating Conditions (Synchronous) ................................... 120

Electrical Specifications – DC Characteristics and Operating Conditions (V

CCQ

) ............................................... 120

Electrical Specifications – AC Characteristics and Operating Conditions (Asynchronous) ................................. 123

Electrical Specifications – AC Characteristics and Operating Conditions (Synchronous) ................................... 125

Electrical Specifications – Array Characteristics .............................................................................................. 128

Asynchronous Interface Timing Diagrams ...................................................................................................... 129

Synchronous Interface Timing Diagrams ........................................................................................................ 140

Revision History ............................................................................................................................................ 162

Rev. F, Production – 1/18 ............................................................................................................................ 162

Rev. E, Production – 3/10 ........................................................................................................................... 162

Rev. D, Production – 1/10 ........................................................................................................................... 162

Rev. C – 9/09 .............................................................................................................................................. 162

Rev. B – 2/09 .............................................................................................................................................. 162

Rev. A – 1/09 .............................................................................................................................................. 163

Micron Confidential and Proprietary

16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND

Features

PDF: CCM005-816717818-10495

Rev. F 1/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

List of Tables

Table 1: Asynchronous and Synchronous Signal Definitions ............................................................................ 10

Table 2: Array Addressing for Logical Unit (LUN) ............................................................................................ 29

Table 3: Asynchronous Interface Mode Selection ............................................................................................ 30

Table 4: Synchronous Interface Mode Selection .............................................................................................. 40

Table 5: Command Set .................................................................................................................................. 52

Table 6: Read ID Parameters for Address 00h .................................................................................................. 57

Table 7: Read ID Parameters for Address 20h .................................................................................................. 57

Table 8: Feature Address Definitions .............................................................................................................. 58

Table 9: Feature Address 01h: Timing Mode .................................................................................................... 60

Table 10: Feature Addresses 10h and 80h: Programmable Output Drive Strength .............................................. 60

Table 11: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ...................................................... 61

Table 12: Feature Addresses 90h: Array Operation Mode ................................................................................. 61

Table 13: Parameter Page Data Structure ........................................................................................................ 64

Table 14: Status Register Definition ................................................................................................................ 74

Table 15: OTP Area Details ............................................................................................................................ 105

Table 16: Error Management Details ............................................................................................................. 110

Table 17: Output Drive Strength Conditions (V

CCQ

= 1.7–1.95V) ...................................................................... 111

Table 18: Output Drive Strength Impedance Values (V

CCQ

= 1.7–1.95V) ........................................................... 111

Table 19: Output Drive Strength Conditions (V

CCQ

= 2.7–3.6V) ....................................................................... 112

Table 20: Output Drive Strength Impedance Values (V

CCQ

= 2.7–3.6V) ............................................................ 112

Table 21: Pull-Up and Pull-Down Output Impedance Mismatch ..................................................................... 113

Table 22: Asynchronous Overshoot/Undershoot Parameters .......................................................................... 114

Table 23: Synchronous Overshoot/Undershoot Parameters ............................................................................ 114

Table 24: Test Conditions for Input Slew Rate ................................................................................................ 115

Table 25: Input Slew Rate (V

CCQ

= 1.7–1.95V) ................................................................................................. 115

Table 26: Test Conditions for Output Slew Rate .............................................................................................. 116

Table 27: Output Slew Rate (V

CCQ

= 1.7–1.95V) ............................................................................................... 116

Table 28: Output Slew Rate (V

CCQ

= 2.7–3.6V) ................................................................................................ 116

Table 29: Absolute Maximum Ratings by Device ............................................................................................ 117

Table 30: Recommended Operating Conditions ............................................................................................. 117

Table 31: Valid Blocks per LUN ...................................................................................................................... 117

Table 32: Capacitance: 100-Ball BGA Package ................................................................................................ 118

Table 33: Capacitance: 48-Pin TSOP Package ................................................................................................. 118

Table 34: Capacitance: 52-Pad LGA Package .................................................................................................. 118

Table 35: Test Conditions .............................................................................................................................. 119

Table 36: DC Characteristics and Operating Conditions (Asynchronous Interface) .......................................... 119

Table 37: DC Characteristics and Operating Conditions (Synchronous Interface) ............................................ 120

Table 38: DC Characteristics and Operating Conditions (3.3V V

CCQ

) ............................................................... 120

Table 39: DC Characteristics and Operating Conditions (1.8V V

CCQ

) ............................................................... 122

Table 40: AC Characteristics: Asynchronous Command, Address, and Data ..................................................... 123

Table 41: AC Characteristics: Synchronous Command, Address, and Data ...................................................... 125

Table 42: Array Characteristics ...................................................................................................................... 128

Micron Confidential and Proprietary

16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND

Features

PDF: CCM005-816717818-10495

Rev. F 1/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.