Fig. 5.30 FT-PHENIC system architecture. a 3 3 mesh-based system,
b 5 5 non-blocking photonic switch, c Unified tile including
PE, NI, and control modules
............................ 150
Fig. 5.31 Microring fault-resilient photonic router (MRPR):
a Non-blocking fault-tolerant photonic switch, b Light-weight
control router
........................................ 152
Fig. 5.32 Example of how a non-re dundant MR’s functionality can be
mimicked by redundant ones
............................ 153
Fig. 5.33 Microring fault-resilient path configuration: a Path setup,
b Path-blocked, c Faulty MR with recovery. GW
0
: Gateway for
data, GW
1
: Gatew ay for acknowledgment signals, PS: photonic
switch, MRCT: Microring Con figuration Table, MRST:
Microring State Table. 00 ¼ Not faulty, Not blocked, 01 ¼ Not
faulty, Blocked, 10 ¼ Faulty
............................ 157
Fig. 5.34 Fault-tolerant path-configuration algorithm
................. 158
Fig. 5.35 Latency comparison results under random unifo rm traffic:
a Overall Latency, b Latency near saturation
............... 163
Fig. 5.36 Latency results of each system as faults are introduced
........ 164
Fig. 5.37 Bandwidth comparison results under random uniform traffic
.... 164
Fig. 5.38 Bandwidth comparison results as faults are introduced
........ 164
Fig. 5.39 Total energy and energy efficiency comparison results under
random uniform traffic near saturation
..................... 165
Fig. 5.40 Total energy and energy efficiency comparison results under
random uniform traffic with 4% of MRs acting faulty
......... 165
Fig. 5.41 Example of photonic switches. From left to right: PHENIC’s
original [9], crossbar, and crux [104]
..................... 167
Fig. 6.1 Reducing footprint and wire length in 3D-stack structure
...... 176
Fig. 6.2 3D integration schemes: a Wire bonding; b Solder balls;
c Through silicon vias; d Wireless stacking
................ 176
Fig. 6.3 TSV fault-tolerance schemes: a Redundancy technique;
b Double TSV; c Network TSV
......................... 178
Fig. 6.4 High-level view of the system architecture with 3 3 3
configuration
........................................ 180
Fig. 6.5 TSV sharing area placement and connectivity between two
neighboring routers
................................... 180
Fig. 6.6 The TSV fault-tolerance architecture: a Router wrapper;
b Connection between two layers. Red rectangles represent
TSVs. S-UP and S-DOWN are the sharing arbitrators which
manage the proposed mechanism. CR stands for configuration
register and W is the flit wi dth
.......................... 181
Fig. 6.7 Adaptive online TSV sharing algorithm
................... 183
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