Designware GMAC IP Ethernet Databook v3.50a - FPGA网络设计参考资料

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Designware GMAC IP（通用媒体访问控制接口）配套硬件手册，即DWCEtherMAC 10/100/1000 Universal和DWCEtherMAC 10/100 Universal，是Synopsys公司于2009年2月发布的版本3.50a。这份文档对于FPGA（现场可编程门阵列）网络设计工程师具有重要价值，它详细介绍了这些MAC（介质访问控制）IP核的功能、工作原理以及在实际应用中的设计指导。该手册的核心内容围绕Ethernet MAC子系统展开，包括但不限于以下几个方面： 1. **MAC架构**：介绍DWCEtherMAC系列的设计特点，可能涵盖了帧的接收、处理、发送过程，以及与物理层（PHY）的交互。这部分内容会深入到数据包的封装和解封装、错误检测与纠正、流量控制和冲突避免等关键功能。 2. **速率支持**：作为10/100/1000 Universal版本，手册将详细说明MAC如何适应不同速率的以太网标准，如10Mbps、100Mbps和1Gbps，以及可能的自适应能力。 3. **协议栈集成**：MAC通常与TCP/IP协议栈集成，手册会阐述MAC如何与IP层进行通信，包括如何处理IP头部、如何实现数据包的封装和拆封，以及如何确保网络层的数据可靠传输。 4. **硬件接口**：文档将提供详细的硬件接口规范，包括输入/输出引脚定义、控制信号说明以及中断机制，以便开发人员能够正确地将MAC IP与FPGA内部其他模块或外部设备连接。 5. **知识产权保护**：版权和专有信息部分强调了用户使用此IP核时必须遵守的法律条款，包括软件许可协议，任何未经书面许可的复制、传播或翻译行为都是禁止的。 6. **出口管制**：由于涉及美国的出口管制法律，手册强调了目的地国家的规定，用户需要确保他们的使用符合美国法律，并遵守相关的出口法规。 7. **免责声明**：最后，Synopsys提供的免责声明表明，虽然文档提供了技术信息，但读者需要自行判断适用的法规并确保其操作符合法规要求。 Designware GMAC IP配套硬件手册是网络设计人员在设计FPGA时的重要参考资料，它涵盖了MAC核心功能的实现、性能优化、以及合规性要求，为高效、安全的网络设计提供了坚实的技术基础。

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16 Synopsys, Inc. February 2009

Preface Ethernet MAC Universal Databook

Customer Support

For customer support:

❖ Enter a call through SolvNet.

✦ Go to https://solvnet.synopsys.com/ManageCase?ccf=1

and provide the requested information, including:

✧ Product: DesignWare Cores

✧ Sub Product: Select 10/100 Ethernet or Gigabit Ethernet.

✧ Version: 3.50a

✧ Subject: Ethernet MAC Universal

❖ Send an e-mail message to support_center@synopsys.com.

✦ Include the Product name, Sub Product name, and Version (product release number) in your

e-mail so it can be routed correctly.

✦ Provide the following additional information, if applicable:

✧ For environment setup problems, run the debug_info command in the coreConsultant GUI

and include the text file generated.

✧ For configuration failures, include the error messages that appear in the coreConsultant GUI

console pane.

✧ For simulation failures, include a text file with your specific configuration. Generate this text

file using the coreConsultant GUI.s write_batch_script command. Also include the log file

from the <workspace>/simulation/ directory, the log file for the specific test, and a

VPD/VCD waveform dump file.

✧ For synthesis failures, include the log file from the <workspace>/syn/ directory.

❖ Telephone your local support center:

✦ United States:

Call 1-800-245-8005 from 7 AM to 5:30 PM Pacific time, Monday through Friday.

✦ Canada:

Call 1-650-584-4200 from 7 AM to 5:30 PM Pacific time, Monday through Friday.

✦ All other countries:

http://www.synopsys.com/Support/GlobalSupportCenters/Pages/default.aspx

February 2009 Synopsys, Inc. 19

Ethernet MAC Universal Databook Product Overview

1.2.2 Interfaces

The GMAC-AHB or GMAC-AXI can be selected based on whether the system is designed with an AHB or

AXI on-chip bus.

The GMAC-AHB transfers data to system memory through the AHB master interface. This interface can be

removed for a non-AHB system, and the subsystem will have a direct native FIFO-type interface. The host

CPU uses the default 32-bit AHB Slave interface to access the GMAC subsystem’s Control and Status

registers (CSRs), when GMAC-AHB is selected. There is an option to select an APB port for CSR access

instead of the AHB Slave port. For non-AHB systems, the AHB/APB slave modules can be removed and the

native 32-bit Read/Write bus is provided for CPU accesses.

The GMAC-AXI transfers data to system memory through the AXI master interface. The host CPU uses the

AXI Slave interface to access the GMAC subsystem’s Control and Status registers (CSRs), when GMAC-AXI

is selected. There is an option to select an APB port for CSR access instead of the AXI Slave port.

The GMAC-UNIV supports any one or a combination of the following PHY interfaces:

❖ Gigabit Media Independent Interface (GMII)/Media Independent Interface (MII) [Default]

❖ Reduced GMII (RGMII)

❖ Serial GMII (SGMII)

❖ Ten Bit Interface (TBI)

❖ Reduced MII (RMII)

❖ Serial MII (SMII)

❖ Reduced TBI (RTBI)

1.2.3 Transmit and Receive FIFOs

The Transmit FIFO (Tx FIFO) buffers data read from system memory by the DMA before transmission by

the GMAC Core. Similarly, the Receive FIFO (Rx FIFO) stores the Ethernet frames received from the line

until they are transferred to system memory by the DMA. These are asynchronous FIFOs, as they also

transfer the data between the application clock and the GMAC line clocks.

Both FIFOs are required to be two-ported RAM of configurable depth (35/68/133 bits wide for 32/64/128

data bus widths).

In the GMAC-MTL configuration, an additional two-port RAM (width configurable from 12 to 15 bits) is

needed to store the frame lengths of received frames in the Rx FIFO. The depth of this frame-length FIFO

depends on the maximum number of frames that can be stored in the Rx FIFO. This frame-length FIFO is

optional, and is disabled by default.

20 Synopsys, Inc. February 2009

Product Overview Ethernet MAC Universal Databook

1.3 Features List

The GMAC-UNIV includes the following features, listed by category.

1.3.1 GMAC Core Features

❖ Supports 10/100/1000-Mbps data transfer rates with the following PHY interfaces

✦ IEEE 802.3-compliant GMII/MII (default) interface to communicate with an external

Gigabit/Fast Ethernet PHY

✦ IEEE 802.3z-compliant Ten-bit Interface (TBI), (optional), with auto-negotiation to communicate

with an external PHY

✦ RGMII/RTBI interface (optional) to communicate with an external gigabit PHY

✦ SGMII interface (optional) to communicate with an external gigabit PHY

❖ Supports both full-duplex and half-duplex operation

✦ Supports CSMA/CD Protocol for half-duplex operation

✦ Supports packet bursting and frame extension in 1000 Mbps half-duplex operation

✦ Supports IEEE 802.3x flow control for full-duplex operation

✦ Optional forwarding of received pause control frames to the user application in full-duplex

operation

✦ Back-pressure support for half-duplex operation

✦ Automatic transmission of zero-quanta pause frame on deassertion of flow control input in full-

duplex operation

❖ Preamble and start-of-frame data (SFD) insertion in Transmit, and deletion in Receive paths

❖ Automatic CRC and pad generation controllable on a per-frame basis

❖ Options for Automatic Pad/CRC Stripping on receive frames

❖ Programmable frame length to support Standard or Jumbo Ethernet frames with sizes up to 16 KB

❖ Programmable InterFrameGap (40-96 bit times in steps of 8)

❖ Supports a variety of flexible address filtering modes:

✦ Up to 31 additional 48-bit perfect (DA) address filters with masks for each byte

✦ Up to 31 48-bit SA address comparison check with masks for each byte

✦ 64-bit Hash filter (optional) for multicast and uni-cast (DA) addresses

✦ Option to pass all multicast addressed frames

✦ Promiscuous mode support to pass all frames without any filtering for network monitoring

✦ Passes all incoming packets (as per filter) with a status report

❖ Separate 32-bit status returned for transmission and reception packets

❖ Supports IEEE 802.1Q VLAN tag detection for reception frames

❖ Separate transmission, reception, and control interfaces to the Application

❖ Configurable big endian and little endian support for transmission and reception data paths

❖ Supports 32/64/128-bit data transfer interface on the system-side

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