Abstract
Image Understanding is becoming a vital feature in ever more applications ranging from
medical diagnostics to autonomous vehicles. Many applications demand for embedded
solutions that integrate into existing systems with tight real-time and power constraints.
Convolutional Neural Networks (CNNs) presently achieve record-breaking accuracies in
all image understanding benchmarks, but have a very high computational complexity.
Embedded CNNs thus call for small and efficient, yet very powerful computing platforms.
This master thesis explores the potential of FPGA-based CNN acceleration and demonstrates
a fully functional proof-of-concept CNN implementation on a Zynq System-on-Chip. The
ZynqNet Embedded CNN is designed for image classification on ImageNet and consists of
ZynqNet CNN, an optimized and customized CNN topology, and the ZynqNet FPGA Accelerator,
an FPGA-based architecture for its evaluation.
ZynqNet CNN is a highly efficient CNN topology. Detailed analysis and optimization of
prior topologies using the custom-designed Netscope CNN Analyzer have enabled a CNN
with
84.5 %
top-5 accuracy at a computational complexity of only
530
million multiply-
accumulate operations. The topology is highly regular and consists exclusively of convolu-
tional layers, ReLU nonlinearities and one global pooling layer. The CNN fits ideally onto the
FPGA accelerator.
The ZynqNet FPGA Accelerator allows an efficient evaluation of ZynqNet CNN. It accelerates
the full network based on a nested-loop algorithm which minimizes the number of arithmetic
operations and memory accesses. The FPGA accelerator has been synthesized using High-
Level Synthesis for the Xilinx Zynq XC-7Z045, and reaches a clock frequency of
200 MHz
with a device utilization of 80 % to 90 %.
Organization of this report
Chapter 1 gives an overview of the current opportunities and
challenges regarding image understanding in embedded systems. The following chap-
ter 2 introduces the central concepts of Convolutional Neural Networks (CNNs) and Field-
Programmable Gate Arrays (FPGAs), as well as a number of CNN topologies and CNN
accelerators from prior work. Chapter 3 dives deep into the analysis, training and opti-
mization of CNN architectures, and presents our customized ZynqNet CNN topology. Next,
chapter 4 shifts the focus onto the design and implementation of our FPGA-based architec-
ture for the evaluation of CNNs, the ZynqNet FPGA Accelerator, and reports lessons learned
from the application of High-Level Synthesis. Finally, chapter 5 presents the performance
results of the overall ZynqNet Embedded CNN system, before the conclusion in chapter 6 puts
these in a bigger perspective.
iii
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