Volume I: RISC-V User-Level ISA V2.2 iii
convention.
• A revised proposal for the C compressed extension, version 1.9.
Preface to Version 2.0
This is the second release of the user ISA specification, and we intend the specification of the
base user ISA plus general extensions (i.e., IMAFD) to remain fixed for future development. The
following changes have been made since Version 1.0 [35] of this ISA specification.
• The ISA has been divided into an integer base with several standard extensions.
• The instruction formats have been rearranged to make immediate encoding more efficient.
• The base ISA has been defined to have a little-endian memory system, with big-endian or
bi-endian as non-standard variants.
• Load-Reserved/Store-Conditional (LR/SC) instructions have been added in the atomic in-
struction extension.
• AMOs and LR/SC can support the release consistency model.
• The FENCE instruction provides finer-grain memory and I/O orderings.
• An AMO for fetch-and-XOR (AMOXOR) has been added, and the encoding for AMOSWAP
has been changed to make room.
• The AUIPC instruction, which adds a 20-bit upper immediate to the PC, replaces the RDNPC
instruction, which only read the current PC value. This results in significant savings for
position-independent code.
• The JAL instruction has now moved to the U-Type format with an explicit destination
register, and the J instruction has been dropped being replaced by JAL with rd=x0. This
removes the only instruction with an implicit destination register and removes the J-Type
instruction format from the base ISA. There is an accompanying reduction in JAL reach, but
a significant reduction in base ISA complexity.
• The static hints on the JALR instruction have been dropped. The hints are redundant with
the rd and rs1 register specifiers for code compliant with the standard calling convention.
• The JALR instruction now clears the lowest bit of the calculated target address, to simplify
hardware and to allow auxiliary information to be stored in function pointers.
• The MFTX.S and MFTX.D instructions have been renamed to FMV.X.S and FMV.X.D,
respectively. Similarly, MXTF.S and MXTF.D instructions have been renamed to FMV.S.X
and FMV.D.X, respectively.
• The MFFSR and MTFSR instructions have been renamed to FRCSR and FSCSR, respec-
tively. FRRM, FSRM, FRFLAGS, and FSFLAGS instructions have been added to individu-
ally access the rounding mode and exception flags subfields of the fcsr.
• The FMV.X.S and FMV.X.D instructions now source their operands from rs1, instead of rs2.
This change simplifies datapath design.
• FCLASS.S and FCLASS.D floating-point classify instructions have been added.
• A simpler NaN generation and propagation scheme has been adopted.
• For RV32I, the system performance counters have been extended to 64-bits wide, with separate
read access to the upper and lower 32 bits.
• Canonical NOP and MV encodings have been defined.
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