RISC-V指令集手册：伯克利开源项目解析

RISC-V

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"RISC-V 指令集是由伯克利大学开发的开放源代码指令集架构，常用于嵌入式系统和物联网芯片的设计。RISC-V Instruction Set Manual Volume I: User-Level ISA 是该指令集的用户级ISA文档，版本2.2，由Andrew Waterman、Krste Asanović等人编辑。该文档详细阐述了RISC-V架构的基本原理和指令集详情。" RISC-V（Reduced Instruction Set Computer，精简指令集计算机）是一种开放的指令集架构，它基于简洁且模块化的设计理念，旨在提供高效能、低功耗和高度可扩展性。与传统的复杂指令集（CISC）相比，RISC-V更注重简化指令，以减少执行时的复杂性和提高执行效率。用户级ISA是RISC-V指令集的一个重要组成部分，它定义了操作系统和应用程序可以直接使用的指令。这份手册详细介绍了这些指令，包括数据处理、控制流、内存访问、运算符以及异常和中断处理等。以下是RISC-V用户级ISA的一些核心概念： 1. **基础指令集**：RISC-V的基础指令集通常包含32位的RV32I，64位的RV64I，以及128位的RV128I。I代表整数指令集，包括算术、逻辑和分支指令。 2. **扩展指令集**：除了基础指令集外，RISC-V还支持多种扩展，如M（乘法和除法）、A（原子操作）、F（单精度浮点）、D（双精度浮点）、Q（quad精度浮点）、C（压缩指令）等。 3. **向量扩展**：在RISC-V架构中，V扩展提供了向量运算能力，适用于高性能计算和机器学习应用。 4. **寄存器结构**：RISC-V使用固定的寄存器数量，例如在RV32I中，有32个通用目的寄存器（GPRs），每个寄存器都是32位宽。 5. **分支预测和跳转**：RISC-V指令集支持条件和无条件分支，以及跳转指令，有助于优化程序流程。 6. **内存模型**：RISC-V的内存模型简单明了，包括加载/存储指令，支持单字节到四字节的对齐访问。 7. **异常和中断处理**：RISC-V提供了一套完整的异常和中断处理机制，允许系统对各种异常情况进行响应。 RISC-V的开放源代码特性使得它在学术界和工业界得到了广泛采用，许多公司和项目选择RISC-V作为其处理器架构的基础，这进一步推动了生态系统的繁荣。由于其设计的灵活性，RISC-V可以适应从微控制器到超级计算机的各种应用需求。随着物联网、嵌入式和边缘计算领域的发展，RISC-V的影响力预计将持续增长。

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4 Volume I: RISC-V User-Level ISA V2.2

RISC processors except with no branch delay slots and with support for optional variable-length

instruction encodings. The base is carefully restricted to a minimal set of instructions suﬃcient

to provide a reasonable target for compilers, assemblers, linkers, and operating systems (with

additional supervisor-level operations), and so provides a convenient ISA and software toolchain

“skeleton” around which more customized processor ISAs can be built.

Each base integer instruction set is characterized by the width of the integer registers and the

corresponding size of the user address space. There are two primary base integer variants, RV32I

and RV64I, described in Chapters 2 and 4, which provide 32-bit or 64-bit user-level address spaces

respectively. Hardware implementations and operating systems might provide only one or both of

RV32I and RV64I for user programs. Chapter 3 describes the RV32E subset variant of the RV32I

base instruction set, which has been added to support small microcontrollers. Chapter 5 describes

a future RV128I variant of the base integer instruction set supporting a ﬂat 128-bit user address

space. The base integer instruction sets use a two’s-complement representation for signed integer

values.

Although 64-bit address spaces are a requirement for larger systems, we believe 32-bit address

spaces will remain adequate for many embedded and client devices for decades to come and will

be desirable to lower memory traﬃc and energy consumption. In addition, 32-bit address spaces

are suﬃcient for educational purposes. A larger ﬂat 128-bit address space might eventually be

required, so we ensured this could be accommodated within the RISC-V ISA framework.

The base integer ISA may be subset by a hardware implementation, but opcode traps and software

emulation by a more privileged layer must then be used to implement functionality not provided

by hardware.

Subsets of the base integer ISA might be useful for pedagogical purposes, but the base has been

deﬁned such that there should be little incentive to subset a real hardware implementation beyond

omitting support for misaligned memory accesses and treating all SYSTEM instructions as a

single trap.

RISC-V has been designed to support extensive customization and specialization. The base integer

ISA can be extended with one or more optional instruction-set extensions, but the base integer

instructions cannot be redeﬁned. We divide RISC-V instruction-set extensions into standard and

non-standard extensions. Standard extensions should be generally useful and should not conﬂict

with other standard extensions. Non-standard extensions may be highly specialized, or may conﬂict

with other standard or non-standard extensions. Instruction-set extensions may provide slightly

diﬀerent functionality depending on the width of the base integer instruction set. Chapter 21

describes various ways of extending the RISC-V ISA. We have also developed a naming convention

for RISC-V base instructions and instruction-set extensions, described in detail in Chapter 22.

To support more general software development, a set of standard extensions are deﬁned to provide

integer multiply/divide, atomic operations, and single and double-precision ﬂoating-point arith-

metic. The base integer ISA is named “I” (preﬁxed by RV32 or RV64 depending on integer reg-

ister width), and contains integer computational instructions, integer loads, integer stores, and

control-ﬂow instructions, and is mandatory for all RISC-V implementations. The standard integer

multiplication and division extension is named “M”, and adds instructions to multiply and divide

values held in the integer registers. The standard atomic instruction extension, denoted by “A”,

adds instructions that atomically read, modify, and write memory for inter-processor synchroniza-

tion. The standard single-precision ﬂoating-point extension, denoted by “F”, adds ﬂoating-point

Volume I: RISC-V User-Level ISA V2.2 5

registers, single-precision computational instructions, and single-precision loads and stores. The

standard double-precision ﬂoating-point extension, denoted by “D”, expands the ﬂoating-point

registers, and adds double-precision computational instructions, loads, and stores. An integer base

plus these four standard extensions (“IMAFD”) is given the abbreviation “G” and provides a

general-purpose scalar instruction set. RV32G and RV64G are currently the default target of our

compiler toolchains. Later chapters describe these and other planned standard RISC-V extensions.

Beyond the base integer ISA and the standard extensions, it is rare that a new instruction will

provide a signiﬁcant beneﬁt for all applications, although it may be very beneﬁcial for a certain

domain. As energy eﬃciency concerns are forcing greater specialization, we believe it is important to

simplify the required portion of an ISA speciﬁcation. Whereas other architectures usually treat their

ISA as a single entity, which changes to a new version as instructions are added over time, RISC-V

will endeavor to keep the base and each standard extension constant over time, and instead layer

new instructions as further optional extensions. For example, the base integer ISAs will continue

as fully supported standalone ISAs, regardless of any subsequent extensions.

With the 2.0 release of the user ISA speciﬁcation, we intend the “RV32IMAFD” and

“RV64IMAFD”base and standard extensions (aka. “RV32G” and “RV64G”) to remain con-

stant for future development.

1.2 Instruction Length Encoding

The base RISC-V ISA has ﬁxed-length 32-bit instructions that must be naturally aligned on 32-bit

boundaries. However, the standard RISC-V encoding scheme is designed to support ISA extensions

with variable-length instructions, where each instruction can be any number of 16-bit instruction

parcels in length and parcels are naturally aligned on 16-bit boundaries. The standard compressed

ISA extension described in Chapter 12 reduces code size by providing compressed 16-bit instructions

and relaxes the alignment constraints to allow all instructions (16 bit and 32 bit) to be aligned on

any 16-bit boundary to improve code density.

Figure 1.1 illustrates the standard RISC-V instruction-length encoding convention. All the 32-bit

instructions in the base ISA have their lowest two bits set to 11. The optional compressed 16-bit

instruction-set extensions have their lowest two bits equal to 00, 01, or 10. Standard instruction-

set extensions encoded with more than 32 bits have additional low-order bits set to 1, with the

conventions for 48-bit and 64-bit lengths shown in Figure 1.1. Instruction lengths between 80 bits

and 176 bits are encoded using a 3-bit ﬁeld in bits [14:12] giving the number of 16-bit words in

addition to the ﬁrst 5×16-bit words. The encoding with bits [14:12] set to 111 is reserved for future

longer instruction encodings.

Given the code size and energy savings of a compressed format, we wanted to build in support

for a compressed format to the ISA encoding scheme rather than adding this as an afterthought,

but to allow simpler implementations we didn’t want to make the compressed format mandatory.

We also wanted to optionally allow longer instructions to support experimentation and larger

instruction-set extensions. Although our encoding convention required a tighter encoding of the

core RISC-V ISA, this has several beneﬁcial eﬀects.

An implementation of the standard G ISA need only hold the most-signiﬁcant 30 bits in

instruction caches (a 6.25% saving). On instruction cache reﬁlls, any instructions encountered

6 Volume I: RISC-V User-Level ISA V2.2

xxxxxxxxxxxxxxaa 16-bit (aa 6= 11)

xxxxxxxxxxxxxxxx xxxxxxxxxxxbbb11 32-bit (bbb 6= 111)

· · ·xxxx xxxxxxxxxxxxxxxx xxxxxxxxxx011111 48-bit

· · ·xxxx xxxxxxxxxxxxxxxx xxxxxxxxx0111111 64-bit

· · ·xxxx xxxxxxxxxxxxxxxx xnnnxxxxx1111111 (80+16*nnn)-bit, nnn6=111

· · ·xxxx xxxxxxxxxxxxxxxx x111xxxxx1111111 Reserved for ≥192-bits

Byte Address: base+4 base+2 base

Figure 1.1: RISC-V instruction length encoding.

with either low bit clear should be recoded into illegal 30-bit instructions before storing in the

cache to preserve illegal instruction exception behavior.

Perhaps more importantly, by condensing our base ISA into a subset of the 32-bit instruc-

tion word, we leave more space available for custom extensions. In particular, the base RV32I

ISA uses less than 1/8 of the encoding space in the 32-bit instruction word. As described in

Chapter 21, an implementation that does not require support for the standard compressed in-

struction extension can map 3 additional 30-bit instruction spaces into the 32-bit ﬁxed-width

format, while preserving support for standard >=32-bit instruction-set extensions. Further, if

the implementation also does not need instructions >32-bits in length, it can recover a further

four major opcodes.

We consider it a feature that any length of instruction containing all zero bits is not legal, as

this quickly traps erroneous jumps into zeroed memory regions. Similarly, we also reserve the

instruction encoding containing all ones to be an illegal instruction, to catch the other common

pattern observed with unprogrammed non-volatile memory devices, disconnected memory buses,

or broken memory devices.

The base RISC-V ISA has a little-endian memory system, but non-standard variants can provide a

big-endian or bi-endian memory system. Instructions are stored in memory with each 16-bit parcel

stored in a memory halfword according to the implementation’s natural endianness. Parcels forming

one instruction are stored at increasing halfword addresses, with the lowest addressed parcel holding

the lowest numbered bits in the instruction speciﬁcation, i.e., instructions are always stored in a

little-endian sequence of parcels regardless of the memory system endianness. The code sequence

in Figure 1.2 will store a 32-bit instruction to memory correctly regardless of memory system

endianness.

We chose little-endian byte ordering for the RISC-V memory system because little-endian sys-

tems are currently dominant commercially (all x86 systems; iOS, Android, and Windows for

ARM). A minor point is that we have also found little-endian memory systems to be more nat-

ural for hardware designers. However, certain application areas, such as IP networking, operate

on big-endian data structures, and so we leave open the possibility of non-standard big-endian

or bi-endian systems.

We have to ﬁx the order in which instruction parcels are stored in memory, independent

of memory system endianness, to ensure that the length-encoding bits always appear ﬁrst in

Volume I: RISC-V User-Level ISA V2.2 7

// Store 32-bit instruction in x2 register to location pointed to by x3.

sh x2, 0(x3) // Store low bits of instruction in first parcel.

srli x2, x2, 16 // Move high bits down to low bits, overwriting x2.

sh x2, 2(x3) // Store high bits in second parcel.

Figure 1.2: Recommended code sequence to store 32-bit instruction from register to memory.

Operates correctly on both big- and little-endian memory systems and avoids misaligned accesses

when used with variable-length instruction-set extensions.

halfword address order. This allows the length of a variable-length instruction to be quickly

determined by an instruction fetch unit by examining only the ﬁrst few bits of the ﬁrst 16-bit

instruction parcel. Once we had decided to ﬁx on a little-endian memory system and instruction

parcel ordering, this naturally led to placing the length-encoding bits in the LSB positions of the

instruction format to avoid breaking up opcode ﬁelds.

1.3 Exceptions, Traps, and Interrupts

We use the term exception to refer to an unusual condition occurring at run time associated with

an instruction in the current RISC-V thread. We use the term trap to refer to the synchronous

transfer of control to a trap handler caused by an exceptional condition occurring within a RISC-V

thread. Trap handlers usually execute in a more privileged environment.

We use the term interrupt to refer to an external event that occurs asynchronously to the current

RISC-V thread. When an interrupt that must be serviced occurs, some instruction is selected to

receive an interrupt exception and subsequently experiences a trap.

The instruction descriptions in following chapters describe conditions that raise an exception dur-

ing execution. Whether and how these are converted into traps is dependent on the execution

environment, though the expectation is that most environments will take a precise trap when an

exception is signaled (except for ﬂoating-point exceptions, which, in the standard ﬂoating-point

extensions, do not cause traps).

Our use of “exception” and “trap” matches that in the IEEE-754 ﬂoating-point standard.

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