FPGA部分动态重配置实例教程

动态重配置

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Partial Reconfiguration

Tutorial

PlanAhead Design Tool

UG743 (v14.5) April 25, 2013

This tutorial document was last validated using the following software version: ISE Design Suite 14.5This tutorial document was last validated using the following software version: ISE Design Suite 14.5This tutorial document was last validated using the following software version: ISE Design Suite 14.5This tutorial document was last validated using the following software version: ISE Design Suite 14.5

If using a later software version, there may be minor differences between the images and results shown inIf using a later software version, there may be minor differences between the images and results shown inIf using a later software version, there may be minor differences between the images and results shown inIf using a later software version, there may be minor differences between the images and results shown in

this document with what you will see in the Design Suite.this document with what you will see in the Design Suite.this document with what you will see in the Design Suite.this document with what you will see in the Design Suite.

Partial Reconfiguration Tutorial www.xilinx.com 2

UG743 (v14.5) April 25, 2013

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Revision History

Date

Version

Revision

04/25/2013

14.5

Validated with Release.

Partial Reconfiguration Tutorial www.xilinx.com 3

UG743 (v14.5) April 25, 2013

Table of Contents

Revision History........................................................................................................................................................... 2

Table of Contents ............................................................................................................................................................ 3

Partial Reconfiguration in PlanAhead ...................................................................................................................... 5

Tutorial Design Description .................................................................................................................................... 5

Project Directory and HDL Design Structure.................................................................................................... 6

Software Tools Flow .................................................................................................................................................. 7

Software Requirements ............................................................................................................................................ 8

Hardware Requirements .......................................................................................................................................... 8

Preparing the Tutorial Design Files ...................................................................................................................... 8

Lab 1: Partial Reconfiguration in PlanAhead ........................................................................................................ 9

Step 1: Synthesizing Netlists from HDL Source (Optional) ......................................................................... 9

Running the Tcl Scripts to Synthesize All Modules ................................................................................... 9

Step 2: Creating a Project ..................................................................................................................................... 10

Step 3: Creating Reconfigurable Partitions and Adding Reconfigurable Modules ........................ 12

Creating a Reconfigurable Partition for U1_RP_Bram ........................................................................... 12

Creating a Reconfigurable Partition for U2_RP_Count ......................................................................... 14

Step 4: Adding Additional Reconfigurable Modules ................................................................................. 15

Adding a Reconfigurable Module to U1_RP_Bram ................................................................................ 15

Adding a Reconfigurable Module to U2_RP_Count ............................................................................... 16

Changing the Active Reconfigurable Module .......................................................................................... 17

Primitives Associated with Reconfigurable Modules ............................................................................ 17

Step 5: Adding Black Box Modules (Optional) ............................................................................................. 18

Adding a Black Box Module to U2_RP_Count .......................................................................................... 18

Step 6: Floorplanning Reconfigurable Partitions ......................................................................................... 20

Creating the AREA_GROUP Range for pblock_U1_RP_Bram .............................................................. 20

Creating an AREA_GROUP Range for pblock_U2_RP_Count .............................................................. 22

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Partial Reconfiguration Tutorial www.xilinx.com 5

UG743 (v14.5) April 25, 2013

Partial Reconfiguration in PlanAhead

This tutorial demonstrates how to create a simple partial reconfiguration (PR) design from

Hardware Description Language (HDL) synthesis through BIT file generation and download.

Xilinx® software tools are used to implement and analyze the design through the PlanAhead™

software. Other tools, such as CORE Generator™ and ChipScope™ Pro, can be used with a partial

reconfiguration design, but are not described in this tutorial.

To benefit from this tutorial, you must be familiar with partial reconfiguration, and have

experience implementing an FPGA design with Xilinx software.

This tutorial covers only a subset of the features in the PlanAhead tool. Additional features are

covered in other tutorials.

After completing this tutorial, you will be able to set up, run, and manage a partial

reconfiguration project using the PlanAhead tool. Specifically, you will learn how to:

 Create a reconfigurable partition (RP).

 Add a reconfigurable module (RM).

 Define Pblock ranges for the reconfigurable partitions.

 Run pr-specific DRC checks.

 Create and implement configurations.

 Verify configuration and generate bit files.

Tutorial Design Description

The FPGA design in this tutorial is targeted to the Virtex®-6 FPGA ML605 Evaluation Board. The

design targets a Virtex-6 xc6vlx240tff1156-1 device. The FPGA device drives the LEDs in

particular sequences depending on which reconfigurable modules are loaded.

The tutorial design contains two reconfigurable partitions:

 One reconfigurable partition contains embedded block RAM.

Reconfiguring the block RAM module with different block RAM data changes the LED

sequence of the eight GPIO LEDs.

 One reconfigurable partition contains just general fabric (Slice) logic.

Reconfiguring this module with different state machine transitions changes the direction

that the four LEDs rotate, either clockwise or counterclockwise.

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