ADV7180：全球NTSC/PAL/SECAM模拟视频解码器

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"ADV7180是一款10位高分辨率的SDTV（标准清晰度电视）视频解码器，特别适合于将模拟基带电视信号转换为数字视频数据。这款芯片具备全球NTSC（北美）、PAL（欧洲及亚洲大部分地区）和SECAM（法国及东欧部分地区）彩色解调功能，确保了对各种电视标准的兼容性。其内部采用4倍过采样技术处理CVBS（复合视频基带信号），以提高图像质量，同时在Y/C（亮度和色差）模式以及YPrPb（YUV颜色空间的分量视频）模式下分别进行2倍过采样，确保每个通道的精确度。此芯片已通过汽车应用认证，意味着它能够在严苛的环境下稳定工作。" ADV7180的关键特性包括： 1. **全球兼容性**：ADV7180设计时考虑到了全球范围内的电视标准，支持NTSC、PAL和SECAM彩色解调，使得该芯片能在任何采用这些标准的地区正常工作。 2. **10位ADC和过采样技术**：它配备了一个10位模数转换器（ADC），通过4倍过采样技术处理CVBS信号，以减少量化噪声，提升图像的清晰度和细节。对于Y/C和YPrPb模式，采用2倍过采样，同样有助于提高图像质量。 3. **多种工作模式**：ADV7180可以处理CVBS、Y/C和YPrPb三种不同类型的输入信号，提供灵活的接口选择，适应不同的视频源。 4. **汽车应用认证**：由于满足了严格的汽车应用要求，ADV7180适用于车载娱乐系统和其他汽车电子设备，能在高温、振动等恶劣条件下保持稳定性能。 5. **数字接口兼容性**：转换后的视频数据与8位ITU-R.656接口标准兼容，这是一个广泛用于数字视频处理的接口，便于与后续的数字信号处理器或显示设备集成。 6. **专利保护和法律声明**：虽然手册中提到的信息是准确可靠的，但Analog Devices公司不对使用该芯片可能产生的任何专利侵权或其他第三方权利侵犯承担责任。用户在使用该芯片时应自行确保不侵犯任何专利或版权。 7. **技术支持和文档**：Analog Devices提供了详细的芯片手册，用户可以通过其官方网站www.analog.com获取最新的规格书、应用笔记和技术支持。 ADV7180在设计上充分考虑了性能、兼容性和可靠性，是将模拟视频转换为数字视频的理想解决方案，特别是在需要处理多种电视标准的场合。通过集成的过采样技术，它可以提供高质量的数字视频输出，适用于各种嵌入式系统和汽车电子应用。

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ADV7180

Rev. F | Page 16 of 116

48-LEAD LQFP

INTRQ

VS/FIELD

DVDD

DGND

GPO2

GPO3

SCLK

SDATA

ALSB

RESET

VFEFN

AVDD

AGND

VREFP

AGND

PVDD

DVDDIO

SFL

DVDDIO

GPO0

GPO1

DGND

NC = NO CONNECT

DGND

LLC

XTAL1

XTAL

DVDD

DGND

PWRDWN

AGND

ELPF

PIN 1

ADV7180

LQFP

TOP VIEW

(Not to Scale)

05700-062

Figure 11. 48-Lead LQFP Pin Configuration

Table 12. 48-Lead LQFP Pin Function Descriptions

Pin No. Mnemonic Type Description

1, 13, 19, 43 DGND G Digital Ground.

2, 4 DVDDIO P Digital I/O Supply Voltage (1.8V to 3.3 V).

3 SFL O

Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the

subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder.

5, 6, 41, 42 GPO0 to GPO3 O General-Purpose Outputs. These pins can be configured via I

C to allow control of external devices.

7 to 12, 20, 22 P7 to P2, P1, P0 O Video Pixel Output Port. See Table 100 for output configuration for 8-bit and 16-bit modes.

14 LLC O

This is a line-locked output clock for the pixel data output by the ADV7180. It is nominally

27 MHz but varies up or down according to video line length.

15, 48 NC No Connect Pins. These pins are not connected internally.

16 XTAL1 O

This pin should be connected to the 28.6363 MHz crystal or left as a no connect if an external 1.8 V,

28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode, the crystal

must be a fundamental crystal.

17 XTAL I

This is the input pin for the 28.6363 MHz crystal, or this pin can be overdriven by an external 1.8 V,

28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.

18, 44 DVDD P Digital Supply Voltage (1.8 V).

PWRDWN

I A logic low on this pin places the ADV7180 in power-down mode.

23, 28, 32 AGND G Analog Ground.

24 ELPF I The recommended external loop filter must be connected to the ELPF pin, as shown in Figure 58.

25 PVDD P PLL Supply Voltage (1.8 V).

26, 27, 33 to 36 A

1 to A

6 I Analog Video Input Channels.

29 VREFP O Internal Voltage Reference Output. See Figure 58 for recommended output circuitry.

30 VREFN O Internal Voltage Reference Output. See Figure 58 for recommended output circuitry.

31 AVDD P Analog Supply Voltage (1.8 V).

RESET

System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset

the ADV7180 circuitry.

38 ALSB I

This pin selects the I

C address for the ADV7180. For ALSB set to Logic 0, the address selected

for a write is 0x40; for ALSB set to Logic 1, the address selected is 0x42.

39 SDATA I/O I

C Port Serial Data Input/Output Pin.

40 SCLK I I

C Port Serial Clock Input. The maximum clock rate is 400 kHz.

45 VS/FIELD O Vertical Synchronization Output Signal/Field Synchronization Output Signal.

INTRQ

Interrupt Request Output. Interrupt occurs when certain signals are detected on the input video

(see Table 108).

47 HS O Horizontal Synchronization Output Signal.

ADV7180

Rev. F | Page 18 of 116

INPUT CONFIGURATION

The following are the two key steps for configuring the

ADV7180 to correctly decode the input video:

1. Use INSEL[3:0] to configure the routing and format decoding

(CVBS, Y/C, or YPrPb). For the 64-lead and 48-lead LQFP,

see Table 13. For the 40-lead and 32-lead LFCSP, see Table 14.

2. If the input requirements are not met using the INSEL[3:0]

options, the analog input muxing section must be configured

manually to correctly route the video from the analog

input pins to the ADC. The standard definition processor

block, which decodes the digital data, should be configured

to process the CVBS, Y/C, or YPrPb format. This is performed

by INSEL[3:0] selection.

CONNECT ANALOG VIDEO

SIGNALS TO ADV7180.

SET INSEL[3:0] TO CONFIGURE

VIDEO FORMAT. USE PREDEFINED

FORMAT/ROUTING.

CONFIGURE ADC INPUTS USING

MANUAL MUXING CONTROL BITS:

MUX_0[2:0], MUX_1[2:0], MUX_2[2:0].

SEE TABLE 15.

REFER TO

TABLE 13

REFER TO

TABLE 14

LQFP-64

LQFP-48

LFCSP-40

LFCSP-32

05700-011

YES

Figure 14. Signal Routing Options

INSEL[3:0], Input Selection, Address 0x00[3:0]

The INSEL bits allow the user to select the input format. They

also configure the standard definition processor core to process

composite (CVBS), S-Video (Y/C), or component (YPrPb) format.

INSEL[3:0] has predefined analog input routing schemes that

do not require manual mux programming (see Table 13 and

Table 1 4). This allows the user to route the various video signal

types to the decoder and select them using INSEL[3:0] only.

The added benefit is that if, for example, the CVBS input is

selected, the remaining channels are powered down.

Table 13. 64-Lead and 48-Lead LQFP INSEL[3:0]

INSEL[3:0] Video Format Analog Input

0000 Composite CVBS input on A

0001 Composite CVBS input on A

0010 Composite CVBS input on A

0011 Composite CVBS input on A

0100 Composite CVBS input on A

0101 Composite CVBS input on A

0110 Y/C (S-Video) Y input on A

C input on A

0111 Y/C (S-Video) Y input on A

C input on A

1000 Y/C (S-Video) Y input on A

C input on A

1001 YPrPb Y input on A

Pb input on A

Pr input on A

1010 YPrPb Y input on A

Pr input on A

Pb input on A

1011 to 1111 Reserved Reserved

Table 14. 40-Lead and 32-Lead LFCSP INSEL[3:0]

INSEL[3:0] Video Format Analog Input

0000 Composite CVBS input on A

0001 to 0010 Reserved Reserved

0011 Composite CVBS input on A

0100 Composite CVBS input on A

0101 R Not used

0110 Y/C (S-Video) Y input on A

C input on A

0111 to 1000 Reserved Reserved

1001 YPrPb Y input on A

Pr input on A

Pb input on A

1010 to 1111 Reserved Reserved

ADV7180

Rev. F | Page 19 of 116

POWER-ON RESET

After power-up, it is necessary to execute a reset operation. For

correct operation,

RESET

should remain deasserted for 5 ms

after power supplies are stable and within specification and

PWRDWN

(not available in 32-lead LFCSP) is asserted.

ANALOG INPUT MUXING

The ADV7180 has an integrated analog muxing section that

allows more than one source of video signal to be connected to

the decoder. Figure 12 and Figure 13 outline the overall structure of

the input muxing provided in the ADV7180.

A maximum of six CVBS inputs can be connected to and

decoded by the 64-lead and 48-lead devices, and a maximum of

three CVBS inputs can be connected to and decoded by the 40-lead

and 32-lead LFCSP devices. As shown in the Pin Configurations

and Function Description section, these analog input pins lie in

close proximity to one another, which requires careful design of

the printed circuit board (PCB) layout. For example, ground

shielding between all signals should be routed through tracks that are

physically close together. It is strongly recommended to connect

any unused analog input pins to AGND to act as a shield.

MAN_MUX_EN, Manual Input Muxing Enable,

Address 0xC4[7]

To configure the ADV7180 analog muxing section, the user

must select the analog input (A

1 to A

6 for the 64-lead LQFP

and 48-lead devices or A

1 to A

3 for the 40-lead and 32-lead

LFCSP devices) that is to be processed by the ADC.

MAN_MUX_EN must be set to 1 to enable the following

muxing blocks:

• MUX0[2:0], ADC Mux Configuration, Address 0xC3[2:0]

• MUX1[6:4], ADC Mux Configuration, Address 0xC3[6:4]

• MUX2[2:0], ADC Mux Configuration, Address 0xC4[2:0]

The three mux sections are controlled by the signal buses MUX0/

MUX1/MUX2[2:0]. Table 15 explains the control words used.

The input signal that contains the timing information (HS and VS)

must be processed by MUX0. For example, in a Y/C input

configuration, MUX0 should be connected to the Y channel

and MUX1 to the C channel. When one or more muxes are not

used to process video, such as the CVBS input, the idle mux and

associated channel clamps and buffers should be powered down

(see the description of Register 0x3A in Table 1 07).

Table 15. Manual Mux Settings for the ADC (MAN_MUX_EN Must be Set to 1)

ADC Connected To ADC Connected To ADC Connected To

MUX0[2:0] LQFP-64 or

LQFP-48

LFCSP-40 or

LFCSP-32

MUX1[2:0] LQFP-64 or

LQFP-48

LFCSP-40 or

LFCSP-32

MUX2[2:0] LQFP-64 or

LQFP-48

LFCSP-40 or

LFCSP-32

000 No connect No connect 000 No connect No connect 000 No connect No connect

001 A

1 A

1 001 No connect No connect 001 No connect No connect

010 A

2 No connect 010 No connect No connect 010 A

2 No connect

011 A

3 No connect 011 A

3 No connect 011 No connect No connect

100 A

4 A

2 100 A

4 A

2 100 No connect No connect

101 A

5 A

3 101 A

5 A

3 101 A

5 A

110 A

6 No connect 110 A

6 No connect

111 No connect No connect 111 No connect No connect 111 No connect No connect

Note the following:

• CVBS can only be processed by MUX0.

• Y/C can only be processed by MUX0 and MUX1.

• YPrPb can only be processed by MUX0, MUX1, and MUX2.

ADV7180

Rev. F | Page 20 of 116

ANTIALIASING FILTERS

The ADV7180 has optional on-chip antialiasing (AA) filters on

each of the three channels that are multiplexed to the ADC (see

Figure 15). The filters are designed for standard definition video

up to 10 MHz bandwidth. Figure 16 and Figure 17 show the

filter magnitude and phase characteristics.

The antialiasing filters are enabled by default and the selection

of INSEL[3:0] determines which filters are powered up at any

given time. For example, if CVBS mode is selected, the filter

circuits for the remaining input channels are powered down to

conserve power. However, the antialiasing filters can be disabled

or bypassed using the AA_FILT_MAN_OVR control.

FILTER 1

FILTER 2

FILTER 3

10-BIT, 86MHz

ADC

MUX BLOCK

SHA A/D

05700-012

ONLY AVAILABLE IN 64-LEAD AND 48-LEAD PACKAGES.

Figure 15. Antialias Filter Configuration

AA_FILT_MAN_OVR, Antialiasing Filter Override,

Address 0xF3[3]

This feature allows the user to override the antialiasing filters

on/off settings, which are automatically selected by INSEL[3:0].

AA_FILT_EN, Antialiasing Filter Enable, Address 0xF3[2:0]

These bits allow the user to enable or disable the antialiasing

filters on each of the three input channels multiplexed to the

ADC. When disabled, the analog signal bypasses the AA filter

and is routed directly to the ADC.

AA_FILT_EN, Address 0xF3[0]

When AA_FILT_EN[0] is 0, AA Filter 1 is bypassed.

When AA_FILT_EN[0] is 1, AA Filter 1 is enabled.

AA_FILT_EN, Address 0xF3[1]

When AA_FILT_EN[1] is 0, AA Filter 2 is bypassed.

When AA_FILT_EN[1] is 1, AA Filter 2 is enabled.

AA_FILT_EN, Address 0xF3[2]

When AA_FILT_EN[2] is 0, AA Filter 3 is bypassed.

When AA_FILT_EN[2] is 1, AA Filter 3 is enabled.

–36

100M

05700-013

FREQUENCY (Hz)

MAGNITUDE (dB)

10k 100k 1M 10M

–4

–8

–12

–16

–20

–24

–28

–32

Figure 16. Antialiasing Filter Magnitude Response

–150

100M

05700-014

FREQUENCY (Hz)

10k 100k 1M 10M

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–140

PHASE (Degrees)

Figure 17. Antialiasing Filter Phase Response

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