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10-Bit, 4× Oversampling

SDTV Video Decoder

ADV7180

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES FEATURES

Qualified for automotive applications Qualified for automotive applications

Worldwide NTSC/PAL/SECAM color demodulation support Worldwide NTSC/PAL/SECAM color demodulation support

One 10-bit ADC, 4× oversampling for CVBS, 2× oversampling

for Y/C mode, and 2× oversampling for YPrPb (per channel)

One 10-bit ADC, 4× oversampling for CVBS, 2× oversampling

for Y/C mode, and 2× oversampling for YPrPb (per channel)

3 video input channels with on-chip antialiasing filter 3 video input channels with on-chip antialiasing filter

CVBS (composite), Y/C (S-Video), and YPrPb (component)

video input support

CVBS (composite), Y/C (S-Video), and YPrPb (component)

video input support

5-line adaptive comb filters and CTI/DNR video

enhancement

5-line adaptive comb filters and CTI/DNR video

enhancement

Mini-TBC functionality provided by adaptive digital line

length tracking (ADLLT), signal processing, and enhanced

FIFO management

Mini-TBC functionality provided by adaptive digital line

length tracking (ADLLT), signal processing, and enhanced

FIFO management

Integrated AGC with adaptive peak white mode Integrated AGC with adaptive peak white mode

Macrovision copy protection detection Macrovision copy protection detection

NTSC/PAL/SECAM autodetection NTSC/PAL/SECAM autodetection

8-bit ITU-R BT.656 YCrCb 4:2:2 output and HS, VS, and FIELD

1.0 V analog input signal range 1.0 V analog input signal range

Full-featured VBI data slicer with teletext support (WST) Full-featured VBI data slicer with teletext support (WST)

Power-down mode and ultralow sleep mode current Power-down mode and ultralow sleep mode current

2-wire serial MPU interface (I

C compatible) 2-wire serial MPU interface (I

C compatible)

Single 1.8 V supply possible Single 1.8 V supply possible

1.8 V analog, 1.8 V PLL, 1.8 V digital, 1.8 V to 3.3 V I/O supply 1.8 V analog, 1.8 V PLL, 1.8 V digital, 1.8 V to 3.3 V I/O supply

−10°C to +70°C commercial temperature grade −10°C to +70°C commercial temperature grade

−40°C to +85°C industrial/automotive qualified temperature

grade

−40°C to +85°C industrial/automotive qualified temperature

grade

−40°C to +125°C temperature grade for automotive qualified −40°C to +125°C temperature grade for automotive qualified

4 package types 4 package types

64-lead, 10 mm × 10 mm, RoHS-compliant LQFP 64-lead, 10 mm × 10 mm, RoHS-compliant LQFP

48-Lead, 7 mm × 7 mm, RoHS-compliant LQFP 48-Lead, 7 mm × 7 mm, RoHS-compliant LQFP

40-lead, 6 mm × 6 mm, RoHS-compliant LFCSP 40-lead, 6 mm × 6 mm, RoHS-compliant LFCSP

32-lead, 5 mm × 5 mm, RoHS-compliant LFCSP 32-lead, 5 mm × 5 mm, RoHS-compliant LFCSP

GENERAL DESCRIPTION GENERAL DESCRIPTION

The ADV7180 automatically detects and converts standard

analog baseband television signals compatible with worldwide

NTSC, PAL, and SECAM standards into 4:2:2 component video

data compatible with the 8-bit ITU-R BT.656 interface standard.

The ADV7180 automatically detects and converts standard

analog baseband television signals compatible with worldwide

NTSC, PAL, and SECAM standards into 4:2:2 component video

data compatible with the 8-bit ITU-R BT.656 interface standard.

The simple digital output interface connects gluelessly to a wide

range of MPEG encoders, codecs, mobile video processors, and

Analog Devices, Inc., digital video encoders, such as the ADV7179.

External HS, VS, and FIELD signals provide timing references

for LCD controllers and other video ASICs, if required. Accurate

10-bit analog-to-digital conversion provides professional quality

The simple digital output interface connects gluelessly to a wide

range of MPEG encoders, codecs, mobile video processors, and

Analog Devices, Inc., digital video encoders, such as the

APPLICATIONS APPLICATIONS

Digital camcorders and PDAs Digital camcorders and PDAs

Low cost SDTV PIP decoders for digital TVs Low cost SDTV PIP decoders for digital TVs

Multichannel DVRs for video security Multichannel DVRs for video security

AV receivers and video transcoding AV receivers and video transcoding

PCI-/USB-based video capture and TV tuner cards PCI-/USB-based video capture and TV tuner cards

Personal media players and recorders Personal media players and recorders

Smartphone/multimedia handsets Smartphone/multimedia handsets

In-car/automotive infotainment units In-car/automotive infotainment units

Rearview camera/vehicle safety systems Rearview camera/vehicle safety systems

FUNCTIONAL BLOCK DIAGRAM FUNCTIONAL BLOCK DIAGRAM

ADV7179.

External HS, VS, and FIELD signals provide timing references

for LCD controllers and other video ASICs, if required. Accurate

10-bit analog-to-digital conversion provides professional quality

5700-001

XTAL1

XTAL

ANALOG

VIDEO

INPUTS

FILTER

DIGITAL

PROCESSING

BLOCK

2D COMB

VBI SLICER

COLOR

DEMOD

SCLK SDATA ALSB RESET PWRDWN

ONLY AVAILABLE ON 64-LEAD PACKAGE AND 48-LEAD PACKAGES.

16-BIT ONLY AVAILABLE ON 64-LEAD PACKAGE.

48-LEAD, 40-LEAD, AND 32-LEAD PACKAGE USES ONE LEAD FOR VS/FIELD.

NOT AVAILABLE ON 32-LEAD PACKAGE.

ONLY AVAILABLE ON 48-LEAD AND 64-LEAD PACKAGES.

10-BIT, 86MHz

ADC

REFERENCE

PLL ADLLT PROCESSING

CLOCK PROCESSING BLOCK

C/CONTROL

MUX BLOCK

FIFOOUTPUT BLOCK

ADV7180

SHA A/D

LLC

SFL

INTRQ

P15 TO P0

8-BIT/16-BIT

PIXEL DATA

FIELD

GPO

Figure 1.

video performance for consumer applications with true 8-bit

data resolution. Three analog video input channels accept standard

composite, S-Video, or component video signals, supporting a

wide range of consumer video sources. AGC and clamp-restore

circuitry allow an input video signal peak-to-peak range to 1.0 V.

Alternatively, these can be bypassed for manual settings.

The line-locked clock output allows the output data rate, timing

signals, and output clock signals to be synchronous, asynchronous, or

line locked even with ±5% line length variation. Output control

signals allow glueless interface connections in many applications.

The ADV7180 is programmed via a 2-wire, serial bidirectional port

C® compatible) and is fabricated in a 1.8 V CMOS process. Its

monolithic CMOS construction ensures greater functionality with

lower power dissipation. LFCSP package options make the decoder

ideal for space-constrained portable applications. The 64-lead

LQFP package is pin compatible with the ADV7181C.

The 48-Lead LQFP, 40-lead LFCSP, and 32-lead LFCSP use one pin to output

VS or FIELD.

ADV7180

Rev. F | Page 2 of 116

TABLE OF CONTENTS

Features .............................................................................................. 1

General Description ......................................................................... 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Introduction ...................................................................................... 4

Analog Front End ......................................................................... 4

Standard Definition Processor ................................................... 4

Functional Block Diagrams ............................................................. 5

Specifications ..................................................................................... 7

Electrical Characteristics ............................................................. 7

Video Specifications ..................................................................... 8

Timing Specifications .................................................................. 9

Analog Specifications ................................................................. 10

Thermal Specifications .............................................................. 10

Absolute Maximum Ratings .......................................................... 11

ESD Caution ................................................................................ 11

Pin Configurations and Function Descriptions ......................... 12

32-Lead LFCSP ........................................................................... 12

40-Lead LFCSP ........................................................................... 13

64-Lead LQFP ............................................................................. 14

48-Lead LQFP ............................................................................. 16

Analog Front End ........................................................................... 17

Input Configuration ................................................................... 18

Power-On

RESET

...................................................................... 19

Analog Input Muxing ................................................................ 19

Antialiasing Filters ..................................................................... 20

Global Control Registers ............................................................... 21

Power-Saving Modes .................................................................. 21

Reset Control .............................................................................. 21

Global Pin Control ..................................................................... 21

Global Status Register .................................................................... 23

Identification ............................................................................... 23

Status 1 ......................................................................................... 23

Autodetection Result .................................................................. 23

Status 2 ......................................................................................... 23

Status 3 ......................................................................................... 23

Video Processor .............................................................................. 24

SD Luma Path ............................................................................. 24

SD Chroma Path ......................................................................... 24

Sync Processing .......................................................................... 25

VBI Data Recovery ..................................................................... 25

General Setup .............................................................................. 25

Color Controls ............................................................................ 27

Clamp Operation ........................................................................ 29

Luma Filter .................................................................................. 30

Chroma Filter .............................................................................. 33

Gain Operation ........................................................................... 34

Chroma Transient Improvement (CTI) .................................. 38

Digital Noise Reduction (DNR) and Luma Peaking Filter ... 39

Comb Filters ................................................................................ 40

IF Filter Compensation ............................................................. 42

AV Code Insertion and Controls ............................................. 43

Synchronization Output Signals ............................................... 45

Sync Processing .......................................................................... 52

VBI Data Decode ....................................................................... 52

C Readback Registers .............................................................. 61

Pixel Port Configuration ............................................................... 74

GPO Control ................................................................................... 75

MPU Port Description ................................................................... 76

C Sequencer .............................................................................. 77

C Register Maps ........................................................................... 78

C Programming Examples ........................................................ 105

64-Lead LQFP ........................................................................... 105

48-Lead LQFP ........................................................................... 106

40-Lead LFCSP ......................................................................... 107

32-Lead LFCSP ......................................................................... 108

PCB Layout Recommendations .................................................. 109

Analog Interface Inputs ........................................................... 109

Power Supply Decoupling ....................................................... 109

PLL ............................................................................................. 109

VREFN and VREFP ................................................................. 109

Digital Outputs (Both Data and Clocks) .............................. 109

Digital Inputs ............................................................................ 109

Typical Circuit Connection ......................................................... 110

Outline Dimensions ..................................................................... 114

Ordering Guide ........................................................................ 116

Automotive Products ............................................................... 116

ADV7180

Rev. F | Page 3 of 116

REVISION HISTORY

7/10—Rev. E to Rev. F

Added 48-Lead LQFP .................................................. Throughout

Changes to Features Section ............................................................ 1

Changes to Table 2 ............................................................................ 4

Added Figure 5; Renumbered Sequentially ................................... 6

Added Input Current (SDA, SCLK) Parameter and Input

Current (

PWRDWN

) Parameter, Table 3 ...................................... 7

Added Figure 11 and Table 12; Renumbered Sequentially ........ 16

Changes to MAN_MUX_EN, Manual Input Muxing Enable,

Address 0xC4[7] Section ................................................................ 19

Added GDE_SEL_OLD_ADF Bit Description, Table 107 ........ 92

Moved 32-Lead LFCSP Section ...................................................108

Added Figure 58 ............................................................................112

Updated Outline Dimensions ......................................................115

Changes to Ordering Guide .........................................................116

2/10—Rev. D to Rev. E

Added 32-Lead LFCSP ................................................ Throughout

Changes to Features .......................................................................... 1

Changes to Figure 1 ........................................................................... 1

Changes to Introduction .................................................................. 4

Added Figure 4, Renumbered Sequentially ................................... 8

Added Figure 9 and Table 11 ......................................................... 14

Changes to Figure 11 ...................................................................... 15

Changes to Table 12 and Table 13 ................................................. 16

Changes to Power-On Reset Section, Analog Input Muxing

Section, and Table 14 ...................................................................... 17

Changes to PDBP Section and TOD Section .............................. 19

Changes to Identification Section ................................................. 21

Changes to VS and FIELD Configuration Section and SQPE

Section .............................................................................................. 44

Changes to Table 99 and Table 100 ............................................... 72

Changes to GPO Control Section ................................................. 73

Changes to Table 104 ...................................................................... 76

Changes to Table 106 ...................................................................... 80

Added Figure 56 ............................................................................108

Added Figure 59 ............................................................................110

Changes to Ordering Guide .........................................................110

6/09—Rev. C to Rev. D

Change to General Description ....................................................... 1

Deleted Comparison with the ADV7181B Section ...................... 5

Deleted Figure 2; Renumbered Sequentially ................................. 5

Changes to Power Requirements Parameter, Table 2 ................... 6

Changes to Table 29 ........................................................................ 25

Changes to Figure 33 ...................................................................... 44

Changes to Subaddress 0x0A Notes, Table 104 ........................... 81

Changes to Ordering Guide .........................................................110

4/09—Rev. B to Rev. C

Changes to Features Section ............................................................ 1

Changes to Absolute Maximum Ratings, Table 7 ....................... 11

Changes to Figure 7 and Table 8, EPAD Addition ...................... 12

Added Power-On

RESET

Section ................................................. 17

Changes to MAN_MUX_EN, Manual Input Muxing Enable,

Address 0xC4[7] Section and Table 12 ......................................... 17

Changes to Identification Section ................................................. 21

Added Table 16; Renumbered Sequentially ................................. 21

Changes to Table 21 ........................................................................ 23

Changes to CIL[2:0], Count Into Lock, Address 0x51[2:0]

Section and COL[2:0], Count Out of Lock, Address 0x51[5:3]

Section .............................................................................................. 25

Changes to Table 32 and Table 33 ................................................. 30

Changes to Table 34 ........................................................................ 32

Changes to Table 42 ........................................................................ 35

Changes to Table 52 ........................................................................ 38

Changes to Table 53 and Table 56 ................................................. 39

Changes to Table 61 and Figure 32 ............................................... 43

Added SQPE, Square Pixel Mode, Address 0x01[2] Section ..... 44

Changes to NEWAVMODE, New AV Mode, Address 0x31[4]

Section .............................................................................................. 44

Changes to Figure 34 ...................................................................... 45

Changes to NFTOG[4:0], NTSC Field Toggle,

Address 0xE7[4:0] Section ............................................................. 47

Changes to PFTOG, PAL Field Toggle, Address 0xEA[4:0]

Section .............................................................................................. 49

Changes to VDP Manuel Configuration Section ....................... 50

Changes to Table 66 ........................................................................ 51

Changes to Table 71 ........................................................................ 54

Changes to Table 72 ........................................................................ 55

Changes to VPS Section and PDC/UTC Section ....................... 63

Changes to Gemstar_2x Format, Half-Byte Output Mode

Section .............................................................................................. 66

Changes to NTSC CCAP Data Section and PAL CCAP Data

Section .............................................................................................. 69

Changes to Figure 48 ...................................................................... 74

Changes to I

C Sequencer Section ................................................ 75

Changes to Table 102 ...................................................................... 76

Changes to Table 104 ...................................................................... 80

Changes to Table 105 ...................................................................... 97

Changes to Figure 53 .................................................................... 108

Changes to Figure 54 .................................................................... 109

Added Exposed Paddle Notation to Outline Dimensions ....... 110

Changes to Ordering Guide ......................................................... 111

2/07—Rev. A to Rev. B

Changes to SFL_INV, Subcarrier Frequency Lock Inversion

Section .............................................................................................. 24

Changes to Table 103, Register 0x41 ............................................ 90

Updated Outline Dimensions ...................................................... 111

11/06—Rev. 0 to Rev. A

Changes to Table 10 and Table 11 ................................................. 16

Changes to Table 30 ........................................................................ 28

Changes to Gain Operation Section ............................................. 33

Changes to Table 43 ........................................................................ 35

Changes to Table 97 ........................................................................ 72

Changes to Table 99 ........................................................................ 73

Changes to Table 103 ...................................................................... 80

Changes to Figure 54 .................................................................... 110

1/06—Revision 0: Initial Version

ADV7180

Rev. F | Page 4 of 116

INTRODUCTION

The ADV7180 is a versatile one-chip multiformat video decoder

that automatically detects and converts PAL, NTSC, and SECAM

standards in the form of composite, S-Video, and component

video into a digital ITU-R BT.656 format.

The simple digital output interface connects gluelessly to a wide

range of MPEG encoders, codecs, mobile video processors, and

Analog Devices digital video encoders, such as the ADV7179.

External HS, VS, and FIELD signals provide timing references

for LCD controllers and other video ASICs that do not support the

ITU-R BT.656 interface standard. The different package options

available for the ADV7180 are shown in Table 2 .

ANALOG FRONT END

The ADV7180 analog front end comprises a single high speed,

10-bit analog-to-digital converter (ADC) that digitizes the

analog video signal before applying it to the standard definition

processor. The analog front end employs differential channels to

the ADC to ensure high performance in mixed-signal applications.

The front end also includes a 3-channel input mux that enables

multiple composite video signals to be applied to the ADV7180.

Current clamps are positioned in front of the ADC to ensure

that the video signal remains within the range of the converter.

A resistor divider network is required before each analog input

channel to ensure that the input signal is kept within the range

of the ADC (see Figure 27). Fine clamping of the video signal

is performed downstream by digital fine clamping within the

ADV7180.

Table 1 shows the three ADC clocking rates that are determined by

the video input format to be processed—that is, INSEL[3:0].

These clock rates ensure 4× oversampling per channel for CVBS

mode and 2× oversampling per channel for Y/C and YPrPb modes.

Table 1. ADC Clock Rates

Input Format ADC Clock Rate (MHz)

Oversampling

Rate per Channel

CVBS 57.27 4×

Y/C (S-Video)

86 2×

YPrPb 86 2×

Based on a 28.6363 MHz crystal between the XTAL and XTAL1 pins.

See INSEL[3:0] in Table 107 for the mandatory write for Y/C (S-Video) mode.

STANDARD DEFINITION PROCESSOR

The ADV7180 is capable of decoding a large selection of baseband

video signals in composite, S-Video, and component formats.

The video standards supported by the video processor include

PAL B/D/I/G/H, PAL 60, PAL M, PAL N, PAL Nc, NTSC M/J,

NTSC 4.43, and SECAM B/D/G/K/L. The ADV7180 can

automatically detect the video standard and process it accordingly.

The ADV7180 has a five-line, superadaptive, 2D comb filter

that gives superior chrominance and luminance separation

when decoding a composite video signal. This highly adaptive filter

automatically adjusts its processing mode according to the video

standard and signal quality without requiring user intervention.

Video user controls such as brightness, contrast, saturation, and

hue are also available with the ADV7180.

The ADV7180 implements a patented ADLLT™ algorithm to

track varying video line lengths from sources such as a VCR.

ADLLT enables the ADV7180 to track and decode poor quality

video sources such as VCRs and noisy sources from tuner outputs,

VCD players, and camcorders. The ADV7180 contains a chroma

transient improvement (CTI) processor that sharpens the edge

rate of chroma transitions, resulting in sharper vertical transitions.

The video processor can process a variety of VBI data services,

such as closed captioning (CCAP), wide screen signaling (WSS),

copy generation management system (CGMS), EDTV, Gemstar®

1×/2×, and extended data service (XDS). Teletext data slicing

for world standard teletext (WST), along with program delivery

control (PDC) and video programming service (VPS), are

provided. Data is transmitted via the 8-bit video output port as

ancillary data packets (ANC). The ADV7180 is fully Macrovision®

certified; detection circuitry enables Type I, Type II, and Type III

protection levels to be identified and reported to the user. The

decoder is also fully robust to all Macrovision signal inputs.

Table 2. ADV7180 Selection Guide

Part Number Package Type Analog Inputs Digital Outputs Temperature Grade

ADV7180KCP32Z 32-lead LFCSP 3 8-bit −10°C to +70°C

ADV7180WBCP32Z (Automotive)

32-lead LFCSP 3 8-bit −40°C to +85°C

ADV7180BCPZ 40-lead LFCSP 3 8-bit −40°C to +85°C

ADV7180WBCPZ (Automotive)

40-lead LFCSP 3 8-bit −40°C to +125°C

ADV7180BSTZ 64-lead LQFP 6 8-bit/16-bit −40°C to +85°C

ADV7180WBSTZ (Automotive)

64-lead LQFP 6 8-bit/16-bit −40°C to +125°C

ADV7180WBST48Z (Automotive)

48-lead LQFP 6 8-bit −40°C to +85°C

Automotive qualification completed.

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