Table of Contents
Foreword ................................................................................................................. xxi
Preface ................................................................................................................... xxiii
Target audience...................................................................................................................... xxiii
Topics covered ........................................................................................................................xxiv
About the examples in this book..............................................................................................xxv
Obtaining copies of the examples ...........................................................................................xxvi
Example testing.......................................................................................................................xxvi
Other sources of information .................................................................................................xxvii
Acknowledgements..................................................................................................................xxx
Chapter 1: Introduction to SystemVerilog...............................................................1
1.1 SystemVerilog origins.......................................................................................................1
1.1.1 Generations of the SystemVerilog standard.......................................................2
1.1.2 Donations to SystemVerilog ..............................................................................4
1.2 Key SystemVerilog enhancements for hardware design...................................................5
1.3 Summary ...........................................................................................................................6
Chapter 2: SystemVerilog Declaration Spaces ........................................................7
2.1 Packages ...........................................................................................................................8
2.1.1 Package definitions ............................................................................................9
2.1.2 Referencing package contents..........................................................................10
2.1.3 Synthesis guidelines .........................................................................................14
2.2 $unit compilation-unit declarations.................................................................................14
2.2.1 Coding guidelines.............................................................................................17
2.2.2 SystemVerilog identifier search rules ..............................................................17
2.2.3 Source code order.............................................................................................17
2.2.4 Coding guidelines for importing packages into $unit......................................19
2.2.5 Synthesis guidelines .........................................................................................25
2.3 Declarations in unnamed statement blocks .....................................................................26
2.3.1 Local variables in unnamed blocks ..................................................................27
2.4 Simulation time units and precision ................................................................................28
2.4.1 Verilog’s timescale directive............................................................................28
2.4.2 Time values with time units .............................................................................30
2.4.3 Scope-level time unit and precision .................................................................31
评论2