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LIST OF TABLES
are opting for computer science or computer engineering courses in preference
to electrical or electronic engineering. SystemVerilog offers a means to interest
computing-oriented students in hardware design. Finally, simulation and synthe-
sis tools and FPGA design kits are now mature and available relatively cheaply to
educational establishments on PC platforms.
Structure of this book
Chapter 1 introduces the ideas behind this book, namely the use of electronic de-
sign automation tools and CMOS and programmable logic technology. We also
consider some engineering problems, such as noise margins and fan-out. In Chap-
ter 2, the principles of Boolean algebra and of combinational logic design are re-
viewed. The important matter of timing and the associated problem of hazards are
discussed. Some basic techniques for representing data are discussed.
SystemVerilog is introduced in Chapter 3 through basic logic gate m odels. The
importance of documented code is emphasized. We show how to construct netlists
of basic gates and how to model delays through gates. We also discuss parameter-
ized models. The idea of using SystemVerilog to verify models with testbenches is
introduced.
In Chapter 4, a variety of modeling techniques are described. Combinational
building blocks, buffers, decoders, encoders, multiplexers, adders and parity check-
ers are modeled using a range of concurrent and sequential SystemVerilog coding
constructs. The SystemVerilog models of hardware introduced in this chapter and
in Chapters 5, 6 and 7 are, in principle, synthesizable, although discussion of ex-
actly what is supported is deferred until Chapter 10. Testbench design styles are
again discussed here. In addition, the IEEE dependency notation is introduced.
Chapter 5 introduces various sequential building blocks: latches, flip-flops,
registers, counters, memory and a sequential multiplier. The same style as Chapter
4 is used, with IEEE dependency notation, testbench design and the introduction
of SystemVerilog coding constructs.
Chapter 6 is probably the most important chapter of the book and discusses
what might be considered the cornerstone of digital design: the design of finite
state machines. The ASM chart notation is used. The design process from ASM
chart to D flip-flops and next state and output logic is described. SystemVerilog
models of state machines are introduced.
In Chapter 7 the concepts of the previous three chapters are combined. The
ASM chart notation is extended to include coupled state machines and registered
outputs, and hence to datapath-controller partitioning. From this, we explain the
idea of instructions in hardware terms and go on to model a very basic micro-
processor in SystemVerilog. This provides a vehicle to introduce interfaces and
packages.
The design of testbenches is discussed in more detail in C hapter 8. After re-
capping the techniques given in earlier chapters, we go on to discuss testbench
