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PCIe_Base_r3 1_Errata_2017-12-13.docx Page 1 of 55

Errata for the

PCI Express

Base Specification

Revision 3.1,

Single Root I/O Virtualization and

Sharing Revision 1.1,

Address Translation and Sharing

Revision 1.1, and M.2 Specification

Revision 1.0

December 13, 2017

Errata for the PCI Express Base Specification Rev. 3.1a,

SR-IOV Rev. 1.1, ATS Rev. 1.1, and M.2 Rev. 1.0

PCIe_Base_r3 1_Errata_2017-12-13.docx Page 3 of 55

Contents

B1 Separate RefClk with Independent SSC (SRIS) Equation 4.3.9 ............5

B208 Spread Spectrum Modulation Slew Rate ...............................................5

A210 M-PCIe Configuration.Update ................................................................8

B211 Root Complex Extended Capability Headers .........................................9

B214 Inference of Electrical Idle ......................................................................10

B215 ACS Source Validation and Bus Number 0 ............................................10

B216 Root Complex Integrated Endpoint Terminology ...................................11

A217 L1 PM Substates: L1.2 Entry Conditions ................................................11

B218 Root Complex and Routing Element Terms ...........................................12

B244 Device Terminology ...............................................................................12

B219 L1 PM Substates: Electrical Idle Terminology ........................................12

B220 LTSSM Disabled to Detect Transition ....................................................13

B224 Malformed TLPs and Disabled VCs .......................................................13

B228 Link Speed Management .......................................................................14

B229 Corrupt Received DLLP .........................................................................15

B230 Loopback ...............................................................................................15

B231 Flow Control Information Tracked by Receiver ......................................16

B233 M.2 Specification: Reference to Link Capabilities register .....................16

B234 WAKE# and OBFF .................................................................................17

B235 Readiness Time Reporting example times .............................................17

B236 SR-IOV: Changing NumVFs or ARI Capable Hierarchy .........................18

B237 SR-IOV: Bus Numbering inside a Root Complex ...................................18

B242 ATS: Terminology: PRG Response PASID Required ............................18

B246 Device Serial Number ............................................................................19

B248 ATS: Page Request Interface and Dirty Bits ..........................................19

B249 Access Control Services for SR-IOV ......................................................21

B250 Enhanced Allocation: Address Maps ......................................................23

B252 Latency Tolerance Reporting (LTR) .......................................................23

B253 LCRC and Sequence Number Rules (TLP Transmitter) ........................24

B254 PCI Express Capability Structure ...........................................................24

B255 Enhanced Allocation: Reserved Encodings ...........................................25

B256 Enhanced Allocation: Virtual Function BEI Ranges ................................25

B257 Lane Equalization Control Register Nomenclature .................................25

B258 Timing Recommendations for Latency Tolerance Reporting .................27

B259 Completion Timeout Mechanism ............................................................29

B260 Slot Power Limit .....................................................................................29

B263 AtomicOp Completion Rules ..................................................................29

B264 PASID Completions ...............................................................................30

B265 SR-IOV: ARI Capable Hierarchy ............................................................31

Errata for the PCI Express Base Specification Rev. 3.1a,

SR-IOV Rev. 1.1, ATS Rev. 1.1, and M.2 Rev. 1.0

Page 4 of 55 PCIe_Base_r3 1_Errata_2017-12-13.docx

C266 LNR Control Register Offset ..................................................................31

C267 Resizable BAR Control Register Name Usage ......................................31

C268 Resizable BAR Capabilities Register Name Usage ...............................31

B269 DC Balance Tracking .............................................................................32

A270 ECR and ECN Process ..........................................................................32

A271 Expanded Resizable BAR: BAR Size field .............................................32

B274 Advisory Non-Fatal .................................................................................33

C275 MFVC term usage ..................................................................................33

B276 DRS and FRS Message Subtype ...........................................................34

B277 ATS: Translation Completion .................................................................35

B278 ATS: Translation Completion Length .....................................................35

B279 ATS: Completions with Multiple Translations .........................................36

B280 ATS: Translation Completion Lower Address Field ................................36

B281 Completer breaking up Responses ........................................................36

B282 Reserved bits in SKP OS Generation Vector .........................................38

B283 Enhanced Allocation ECN: Enhanced Allocation Capability ...................39

B284 VF Resizable Bar: VF BAR Size ............................................................42

B285 PASID TLP Prefix ...................................................................................43

B286 Multi-Function Arbitration Model Example ..............................................45

B288 Flow Control for Nullified TLPs ...............................................................45

B289 Clarification of HwInit .............................................................................46

B292 Capturing Device Number ......................................................................46

B293 DPC Header Log ....................................................................................47

B294 Completion Handling Rules for ID Based Ordering ................................47

B295 Downstream Port Containment Clarifications .........................................47

B297 ATS: Clarifications ..................................................................................49

B299 PCI Local Bus and SR-IOV: Vendor, Device, and Revision IDs .............50

B300 PME Generation .....................................................................................52

B301 PCI Express Capability Structure ...........................................................54

B303 Hierarchy ID ECN: Hierarchy ID Message .............................................55

Note on Errata Titles and Errata Numbering

Red text in the errata title indicates the affected document(s). Absence of red text means PCI

Express Base Revision 3.1a.

Errata numbering is arbitrary and reflects numbers used during the development process.

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