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1
TimeQuest User Guide
Wiki Release 1.1 December 9th 2010 By: Ryan Scoville
Introduction:
I have spent a good amount of time over the last few years helping designers with
TimeQuest, and found myself writing emails and small documents explaining similar concepts
over and over again. This includes answering questions on www.alteraforum.com under the user
name rysc. This document is an effort to consolidate most of what I’ve learned about TimeQuest
into a single source. It is a work in progress, and currently has significant sections missing. I
hope to be updating this regularly, but am finding the more I enter, the more gaps there are.
Right now the core information is there and has more than enough for most users. Looking at
the page count, some might say there is too much information.
Recommendations:
1) Use the Bookmarks when viewing this document, to show the major points and allow
for easy navigation. Examples seem to constantly require an explanation from another section. I
added hyperlinks throughout the document, but I believe the Table of Contents/Bookmarks will
help users navigate the content.
2) Read the first section, Getting Started. I tried to pack as much useful information that
most designers need. Even if you have a good grasp on TimeQuest, it’s probably worth a quick
run through.
3) Read as much of this document as you can. Hopefully this helps the user get "the big
picture" of static timing analysis, rather than only a small sub-section. User's that immediately
jump to an example that is similar to their own often miss the many facets of static timing
analysis, and are more likely to become frustrated or, worse yet, make mistakes.
4) Use TimeQuest. I've seen many users do the opposite of the last recommendation,
where they pour over documentation, trying to understand every nuance of every sentence and
screenshot before opening the tool. As much as I would like users to read everything, it's just as
important to start adding SDC constraints to your design, running TimeQuest, and analyzing
what happens. By the end of the Getting Started section, the user should have most of their core
timing constraints entered, possibly some I/O constraints, and a good handle on timing analysis.
Contact:
TimeQuest support is not my primary responsibility, and so I will not be able to directly
assist users. That being said, if there is anything ambiguous, incorrect, or missing, please contact
me via www.alteraforum.com, sending an email to user Rysc. I also monitor the forum a good
amount and will try to answer questions there, as I much prefer helping with issues on the forum
rather than direct email, since it can hopefully help multiple users. If you post something and I
don’t respond, feel free to send me an email through the forum. That being said, if I am unable
to respond, please don’t be offended.
© 2010 Altera Corporation. The material in this wiki page or document is provided AS-IS and is
not supported by Altera Corporation. Use the material in this document at your own risk; it might
be, for example, objectionable, misleading or inaccurate.
2
Table of Contents
SECTION 1: GETTING STARTED .......................................................................................................................... 5
QUARTUS SETUP ........................................................................................................................................................ 5
CORE TIMING ............................................................................................................................................................ 7
create_clock ......................................................................................................................................................... 7
derive_pll_clocks ................................................................................................................................................. 9
derive_clock_uncertainty ................................................................................................................................... 10
set_clock_groups ................................................................................................................................................ 10
Quick tip for writing set_clock_groups constraint .......................................................................................................... 12
I/O TIMING .............................................................................................................................................................. 14
Step 1) Use create_clock to add a virtual clock for the I/O interface ................................................................ 14
Step 2) Add set_input_delay or set_output_delay on the I/O port/s .................................................................. 15
Step 3) Determine the default setup and hold relationship between the FPGA clock and virtual clock ........... 16
Step 4) Add multicycles ..................................................................................................................................... 18
Step 5) Modify the -max and -min delays to account for external delays. .......................................................... 19
ANALYZING RESULTS .............................................................................................................................................. 22
The Iterative Methodology ................................................................................................................................. 23
A diving tool ....................................................................................................................................................... 25
report_timing ..................................................................................................................................................... 26
Correlating Constraints to the Timing Report ................................................................................................... 29
SECTION 2: TIMING ANALYSIS BASICS ......................................................................................................... 31
BASICS OF SETUP, HOLD, RECOVERY AND REMOVAL ............................................................................................. 31
DEFAULT RELATIONSHIPS ....................................................................................................................................... 35
Determining Default Setup and Hold Relationships in Three Steps................................................................... 35
Points of Interest for Default Relationships ....................................................................................................... 41
Falling Edge Analysis ..................................................................................................................................................... 42
Periodicity ....................................................................................................................................................................... 44
Relationships between Unrelated Clocks ........................................................................................................................ 45
Phase-Shift Affect on Setup and Hold ............................................................................................................................ 47
MULTICYCLES ......................................................................................................................................................... 48
Determining Multicycle Relationships in Five Steps .......................................................................................... 49
Multicycles - Two Common Cases ..................................................................................................................... 55
Case 1 - Opening the Window ........................................................................................................................................ 55
Case 2 - Shifting the Window ......................................................................................................................................... 57
MAX AND MIN DELAYS ........................................................................................................................................... 58
The Dangers of set_max_delay and set_min_delay ........................................................................................... 59
Using set_max_delay and set_min_delay for Tsu, Th, Tco, Min Tco and Tpd ................................................... 61
RECOVERY AND REMOVAL ...................................................................................................................................... 66
SECTION 3: SDC CONSTRAINTS ........................................................................................................................ 73
CREATE_CLOCK ....................................................................................................................................................... 73
CREATE_GENERATED_CLOCK .................................................................................................................................. 74
How Generated Clocks are Analyzed ................................................................................................................. 76
DERIVE_PLL_CLOCKS .............................................................................................................................................. 77
DERIVE_CLOCK_UNCERTAINTY ............................................................................................................................... 78
DERIVE_CLOCKS ...................................................................................................................................................... 78
SET_CLOCK_GROUPS ............................................................................................................................................... 78
SET_MULTICYCLE_PATH .......................................................................................................................................... 80
GET_FANOUTS ......................................................................................................................................................... 83
SET_MAX_DELAY/SET_MIN_DELAY ......................................................................................................................... 84
SET_FALSE_PATH ..................................................................................................................................................... 85
SET_CLOCK_UNCERTAINTY ..................................................................................................................................... 86
3
SET_CLOCK_LATENCY ............................................................................................................................................. 86
SET_INPUT_DELAY/SET_OUTPUT_DELAY ................................................................................................................ 87
SET_MAX_SKEW ...................................................................................................................................................... 89
CONSTRAINT PRIORITY ............................................................................................................................................ 91
Priority between Different Constraints .............................................................................................................. 92
Priority between Equal Constraints ................................................................................................................... 93
Priority between Multiple Assignments to the Same Node ................................................................................. 93
Priority between Derived Assignments and User Assignments .......................................................................... 94
SECTION 4: THE TIMEQUEST GUI .................................................................................................................... 96
ENTERING SDC CONSTRAINTS FROM THE GUI........................................................................................................ 96
GETTING STARTED - TIMING NETLISTS AND SDCS .................................................................................................. 99
MAJOR REPORTS ................................................................................................................................................... 100
DEVICE SPECIFIC REPORTS .................................................................................................................................... 102
Report TCCS .................................................................................................................................................... 102
Report RSKM ................................................................................................................................................... 102
Report DDR ..................................................................................................................................................... 103
Report Metastability ......................................................................................................................................... 103
REPORT_TIMING - IF YOU ONLY KNOW ONE COMMAND… ...................................................................................... 104
TQ_Analysis.tcl ................................................................................................................................................ 104
-false_path ........................................................................................................................................................ 106
Path Filters ...................................................................................................................................................... 106
DATASHEET REPORTS ............................................................................................................................................ 107
Report Fmax ..................................................................................................................................................... 107
Report Datasheet .............................................................................................................................................. 107
DIAGNOSTIC .......................................................................................................................................................... 109
report_clocks .................................................................................................................................................... 109
report_clock_transfers ..................................................................................................................................... 109
Report Unconstrained Paths - report_ucp ....................................................................................................... 110
report_sdc ........................................................................................................................................................ 111
Report Ignored Constraints - “report_sdc -ignored” ...................................................................................... 113
check_timing .................................................................................................................................................... 113
report_partitions .............................................................................................................................................. 116
CUSTOM REPORTS ................................................................................................................................................. 116
Report Timing .................................................................................................................................................. 116
Report Minimum Pulse Width .......................................................................................................................... 116
Report False Path ............................................................................................................................................ 116
Report Path/Report Net .................................................................................................................................... 116
Report Exceptions ............................................................................................................................................ 117
Report Skew and Report Max Skew .................................................................................................................. 117
Report Bottlenecks ........................................................................................................................................... 117
Create Slack Histogram ................................................................................................................................... 118
MACROS ................................................................................................................................................................ 119
Report All Summaries ...................................................................................................................................... 119
Report Top Failing Paths ................................................................................................................................. 119
Report All I/O Timings ..................................................................................................................................... 119
Report All Core Timing .................................................................................................................................... 120
Create All Clock Histograms ........................................................................................................................... 120
SECTION 5: TIMING MODELS .......................................................................................................................... 121
WHY TIMING MODELS ARE IMPORTANT ................................................................................................................ 121
TIMING MODELS .................................................................................................................................................... 123
UNCERTAINTY ....................................................................................................................................................... 124
RISE/FALL VARIATION .......................................................................................................................................... 124
UNATENESS ........................................................................................................................................................... 125
ON-DIE VARIATION ............................................................................................................................................... 127
4
COMMON CLOCK PATH PESSIMISM ....................................................................................................................... 128
SECTION 6: QUARTUS II AND TIMING CONSTRIANTS ............................................................................. 132
SECTION 7: TCL SYNTAX FOR SDC AND ANALYSIS SCRIPTS ............................................................... 132
SECTION 8: COMMON STRUCTURES AND CIRCUITS ............................................................................... 132
PLLS ..................................................................................................................................................................... 132
TRANSCEIVERS ...................................................................................................................................................... 132
LVDS .................................................................................................................................................................... 132
MEMORY INTERFACES ........................................................................................................................................... 132
CLOCK MUXES ...................................................................................................................................................... 132
RIPPLE CLOCKS ..................................................................................................................................................... 132
CLOCK ENABLES ................................................................................................................................................... 132
SECTION 9: EXAMPLES ...................................................................................................................................... 132
SECTION 10: MISCELLANEOUS ....................................................................................................................... 133
STRATEGIES FOR FALSE PATHS.............................................................................................................................. 133
ANALYZING PATHS ................................................................................................................................................ 133
COMPARING SET_INPUT_DELAY/SET_OUTPUT_DELAY TO TSU/TH/TCO AND MIN TCO .......................................... 133
5
Section 1: Getting Started
This first section is meant to get a user up and running as quickly as possible. It touches
on multiple topics that are detailed later, and is meant for application and a quick understanding.
That being said, I think all users should look through this section and make sure they understand
it.
The last portion of Getting Started covers analyzing results, which is an integral part of
entering constraints. One can't enter core timing or I/O constraints without being able to read the
analysis reports, so it is recommended to read that section in conjunction with the information at
the beginning.
Quartus Setup
Within Quartus, there are a number of quick steps for setting up your design with
TimeQuest. These are accessed through the pull-down menu Assignments -> Settings:
1) Along the left panel, select Timing Analysis Settings and select the "Use TimeQuest…" radio
button. The Classic Timing Analyzer is the old timing analysis engine, which is not
recommended for any new designs or architectures, and will eventually become obsolete.
2) Select TimeQuest Timing Analyzer in the left panel. The screenshot should look like below,
whereby the user can add a new SDC file. SDC stands for Synopsys Design Constraint, which is
the format TimeQuest uses, along with many other tools. If no .sdc file exists, we will create it
in the next section. Note that SDC files are analyzed in the order listed, top to bottom.
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