©Copyright 2002-2011 SD Association
SD Host Controller Simplified Specification Version 3.00
iv
Table of Contents
1. Overview of the SD Standard Host ........................................................................................................1
1.1 Scope of the Standard SD Host........................................................................................................1
1.2 Register Map ......................................................................................................................................2
1.3 Multiple Slot Support.........................................................................................................................3
1.4 Supporting DMA.................................................................................................................................3
1.5 SD Command Generation .................................................................................................................4
1.6 Suspend and Resume Mechanism...................................................................................................4
1.7 Buffer Control ....................................................................................................................................5
1.7.1 Control of Buffer Pointer................................................................................................................5
1.7.2 Determining Buffer Block Length...................................................................................................7
1.7.3 Dividing Large Data Transfer.........................................................................................................7
1.8 Relationship between Interrupt Control Registers .........................................................................8
1.9 HW Block Diagram and Timing Part...............................................................................................10
1.10 Power State Definition of SD Host Controller.............................................................................. 11
1.11 Auto CMD12....................................................................................................................................12
1.12 Controlling SDCLK ........................................................................................................................13
1.13 Advanced DMA...............................................................................................................................14
1.13.1 Block Diagram of ADMA2..........................................................................................................14
1.13.2 An Example of ADMA2 Programming........................................................................................ 15
1.13.3 Data Address and Data Length Requirements .......................................................................... 15
1.13.4 Descriptor Table ........................................................................................................................16
1.13.5 ADMA2 States ...........................................................................................................................17
1.14 Test Registers ................................................................................................................................18
1.15 Block Count....................................................................................................................................18
1.16 Sampling Clock Tuning .................................................................................................................18
2. SD Host Standard Register...................................................................................................................19
2.1 Summary of register set..................................................................................................................19
2.1.1 SD Host Control Register Map ....................................................................................................19
2.1.2 Configuration Register Types ......................................................................................................20
2.1.3 Register Initial Values..................................................................................................................20
2.1.4 Reserved Bits of Register............................................................................................................20
2.2 SD Host Standard Register .............................................................................................................21
2.2.1 SDMA System Address / Argument 2 Register (Offset 000h)...................................................... 21
2.2.2 Block Size Register (Offset 004h) ............................................................................................... 22
2.2.3 Block Count Register (Offset 006h).............................................................................................24
2.2.4 Argument 1 Register (Offset 008h)..............................................................................................25
2.2.5 Transfer Mode Register (Offset 00Ch) ........................................................................................26
2.2.6 Command Register (Offset 00Eh) ...............................................................................................29
2.2.7 Response Register (Offset 010h)................................................................................................31
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